RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Memory and bus architecture Table 2. STM32F4xx register boundary addresses (continued) Boundary address Peripheral Bus Register map 0x4001 5400 - 0x4001 57FF SPI6 0x4001 5000 - 0x4001 53FF SPI5 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 APB2 Section 27.5.10: SPI register map on page 841 Section 16.6.11: TIM10/11/13/14 register map on page 520 0x4001 4000 - 0x4001 43FF TIM9 APB2 Section 16.5.14: TIM9/12 register map on page 510 0x4001 3C00 - 0x4001 3FFF EXTI Section 10.3.7: EXTI register map on page 261 0x4001 3800 - 0x4001 3BFF SYSCFG Section 7.2.8: SYSCFG register maps on page 157 0x4001 3400 - 0x4001 37FF SPI4 APB2 Section 27.5.10: SPI register map on page 841 0x4001 3000 - 0x4001 33FF SPI1 Section 27.5.10: SPI register map on page 841 0x4001 2C00 - 0x4001 2FFF SDIO Section 28.9.16: SDIO register map on page 897 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 Section 11.13.18: ADC register map on page 303 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF USART6 USART1 APB2 Section 26.6.8: USART register map on page 789 0x4001 0400 - 0x4001 07FF TIM8 Section 14.4.21: TIM1&TIM8 register map on 0x4001 0000 - 0x4001 03FF TIM1 page 416 0x4000 7C00 - 0x4000 7FFF 0x4000 7800 - 0x4000 7BFF UART8 UART7 APB1 Section 26.6.8: USART register map on page 789 Doc ID 018909 Rev 3 54/1416
Memory and bus architecture <strong>RM0090</strong> Table 2. STM32F4xx register boundary addresses (continued) Boundary address Peripheral Bus Register map 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR Section : on page 110 55/1416 Doc ID 018909 Rev 3 Section 12.5.15: DAC register map on page 325 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF CAN2 CAN1 Section 24.9.5: bxCAN register map on page 700 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 Section 25.6.11: I2C register map on page 737 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF 0x4000 4800 - 0x4000 4BFF UART4 USART3 Section 26.6.8: USART register map on page 789 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF SPI3 / I2S3 SPI2 / I2S2 APB1 Section 27.5.10: SPI register map on page 841 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG Section 18.4.5: IWDG register map on page 536 0x4000 2C00 - 0x4000 2FFF WWDG Section 19.6.4: WWDG register map on page 543 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers Section 23.6.21: RTC register map on page 657 0x4000 2000 - 0x4000 23FF TIM14 Section 16.6.11: TIM10/11/13/14 register map on 0x4000 1C00 - 0x4000 1FFF TIM13 page 520 0x4000 1800 - 0x4000 1BFF TIM12 Section 16.5.14: TIM9/12 register map on page 510 0x4000 1400 - 0x4000 17FF TIM7 Section 17.4.9: TIM6&TIM7 register map on 0x4000 1000 - 0x4000 13FF TIM6 page 531 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF TIM4 TIM3 Section 15.4.21: TIMx register map on page 476 0x4000 0000 - 0x4000 03FF TIM2
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RM0090 Reference manual STM32F40x,
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 case,
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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RM0090: Reference manual - STMicroelectronics

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