RM0090: Reference manual - STMicroelectronics

RM0090 Serial peripheral interface (SPI)
LSB justified standard
This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit
full-accuracy frame formats).
Figure 297. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0
CK
WS
SD
MSB LSB MSB
Channel left
Figure 298. LSB Justified 24-bit frame length with CPOL = 0
CK
WS
SD
Transmission Reception
May be 16-bit, 32-bit
8-bit data
0 forced
Channel left 32-bit
24-bit remaining
MSB LSB
● In transmission mode:
If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register
are required from software or by DMA. The operations are shown below.
Figure 299. Operations required to transmit 0x3478AE
First write to Data register
conditioned by TXE = ‘1’
Transmission Reception
0xXX34 0x78AE
Only the 8 LSB bits of the half-word
are significant. Whatever the 8 MSBs
a field of 0x00 is forced instead
Channel right
Channel right
Second write to Data register
conditioned by TXE = ‘1’
● In reception mode:
If data 0x3478AE are received, two successive read operations from SPI_DR are
required on each RXNE event.
Doc ID 018909 Rev 3 822/1416