RM0090: Reference manual - STMicroelectronics

Serial peripheral interface (SPI) RM0090
It will be: I 2 S bitrate = 32 x 2 x F S if the packet length is 32-bit wide.
Figure 305. Audio sampling frequency definition
sampling point
16-bit or 32-bit Left channel 16-bit or 32-bit Right channel
F S: Audio sampling frequency
32-bits or 64-bits
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 306. I 2 S clock generator architecture
I2SxCLK
8-bit Linear
Divider +
reshaping stage
MCKOE ODD I2SDIV[7:0]
1. Where x could be 2 or 3.
Figure 305 presents the communication clock architecture. To achieve high-quality audio
performance, the I2SxCLK clock source can be either the PLLI2S output (through R division
factor) or an external clock (mapped to I2S_CKIN pin).
The audio sampling frequency can be 192 kHz, 96 kHz, or 48 kHz. In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
FS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
FS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
When the master clock is disabled (MCKOE bit cleared):
FS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
FS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
Table 123 provides example precision values for different clock configurations.
Note: Other configurations are possible that allow optimum clock precision.
825/1416 Doc ID 018909 Rev 3
F S
Divider by 4
I2SMOD
Div2
sampling point
0
1
0
1
MCKOE
CHLEN
MCK
CK