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<strong>RM0090</strong> Hash processor (HASH) 22 Hash processor (HASH) This section applies to the whole STM32F4xx family, unless otherwise specified. 22.1 HASH introduction The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications. It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for messages of up to (2 64 – 1) bits, while HMAC algorithms provide a way of authenticating messages by means of hash functions. HMAC algorithms consist in calling the SHA-1, SHA-224, SHA-256 or MD5 hash function twice. 22.2 HASH main features ● Suitable for data authentication applications, compliant with: – FIPS PUB 180-2 (Federal Information Processing Standards Publication 180-2) – Secure Hash Standard specifications (SHA-1, SHA-224 and SHA-256) – IETF RFC 1321 (Internet Engineering Task Force Request For Comments number 1321) specifications (MD5) ● Fast computation of SHA-1, SHA-224 and SHA-256, and MD5 (SHA-224 and SHA-256 are available on STM32F42x and STM32F43x only) ● AHB slave peripheral ● 32-bit data words for input data, supporting word, half-word, byte and bit bit-string representations, with little-endian data representation only. ● Automatic swapping to comply with the big-endian SHA1, SHA-224 and SHA-256 computation standard with little-endian input bit-string representation ● Automatic padding to complete the input bit string to fit modulo 512 (16 × 32 bits) message digest computing ● 5× 32-bit words (H0 to H5) on STM32F40x and STM32F41x and 8 × 32-bit words (H0 to H7) on STM32F42x and STM32F43x for output message digest, reload able to continue interrupted message digest computation. ● Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the digest of the whole message ● Automatic data flow control with support for direct memory access (DMA) Note: Padding, as defined in the SHA-1, SHA-224 and SHA-256 algorithm, consists in adding a bit at bx1 followed by N bits at bx0 to get a total length congruent to 448 modulo 512. After this, the message is completed with a 64-bit integer which is the binary representation of the original message length. For this hash processor, the quanta for entering the message is a 32-bit word, so an additional information must be provided at the end of the message entry, which is the number of valid bits in the last 32-bit word entered. Doc ID 018909 Rev 3 594/1416
Hash processor (HASH) <strong>RM0090</strong> 22.3 HASH functional description Figure 1 shows the block diagram of the hash processor. Figure 218. Block diagram for STM32F40x and STM32F41x Control and status registers Interrupt registers HASH_IMR HASH_SR Control register HASH_CR Start register HASH_ST R Context swapping HASH_CSR0..50 Message digest HASH_H0...H4 32-bit AHB2 bus context digest Data register 595/1416 Doc ID 018909 Rev 3 HASH_DIN 16 × 32-bit IN FIFO swa ppin g IN buffer SHA-1 / MD5 Hash / HMAC processor core write into HASH_DIN or write DCAL bit to 1 or 1 complete block transferred by the DMA IN FIFO full or DCAL written to 1 ai16081
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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Basic timers (TIM6&TIM7) RM0090 17.
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 19.6
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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