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RM0090: Reference manual - STMicroelectronics

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Ethernet (ETH): media access control (MAC) with DMA controller <strong>RM0090</strong><br />

● Option to filter all error frames on reception and not forward them to the application in<br />

Store-and-Forward mode<br />

● Option to forward under-sized good frames<br />

● Supports statistics by generating pulses for frames dropped or corrupted (due to<br />

overflow) in the Receive FIFO<br />

● Supports Store and Forward mechanism for transmission to the MAC core<br />

● Automatic generation of PAUSE frame control or back pressure signal to the MAC core<br />

based on Receive FIFO-fill (threshold configurable) level<br />

● Handles automatic retransmission of Collision frames for transmission<br />

● Discards frames on late collision, excessive collisions, excessive deferral and underrun<br />

conditions<br />

● Software control to flush Tx FIFO<br />

● Calculates and inserts IPv4 header checksum and TCP, UDP, or ICMP checksum in<br />

frames transmitted in Store-and-Forward mode<br />

● Supports internal loopback on the MII for debugging<br />

29.2.2 DMA features<br />

● Supports all AHB burst types in the AHB Slave Interface<br />

● Software can select the type of AHB burst (fixed or indefinite burst) in the AHB Master<br />

interface.<br />

● Option to select address-aligned bursts from AHB master port<br />

● Optimization for packet-oriented DMA transfers with frame delimiters<br />

● Byte-aligned addressing for data buffer support<br />

● Dual-buffer (ring) or linked-list (chained) descriptor chaining<br />

● Descriptor architecture, allowing large blocks of data transfer with minimum CPU<br />

intervention;<br />

● each descriptor can transfer up to 8 KB of data<br />

● Comprehensive status reporting for normal operation and transfers with errors<br />

● Individual programmable burst size for Transmit and Receive DMA Engines for optimal<br />

host bus utilization<br />

● Programmable interrupt options for different operational conditions<br />

● Per-frame Transmit/Receive complete interrupt control<br />

● Round-robin or fixed-priority arbitration between Receive and Transmit engines<br />

● Start/Stop modes<br />

● Current Tx/Rx Buffer pointer as status registers<br />

● Current Tx/Rx Descriptor pointer as status registers<br />

29.2.3 PTP features<br />

● Received and transmitted frames time stamping<br />

● Coarse and fine correction methods<br />

● Trigger interrupt when system time becomes greater than target time<br />

● Pulse per second output (product alternate function output)<br />

901/1416 Doc ID 018909 Rev 3

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