RM0090: Reference manual - STMicroelectronics

RM0090 Flexible static memory controller (FSMC)
Figure 416. Multiplexed write accesses
A[25:16]
NADV
NEx
NOE
NWE
AD[15:0]
The difference with mode D is the drive of the lower address byte(s) on the databus.
Table 207. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-16 0x0000
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x0
13-10 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 -
6 FACCEN 0x1
5-4 MWID As needed
3-2 MTYP 0x2 (NOR)
1 MUXEN 0x1
0 MBKEN 0x1
Table 208. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31-20 0x0000
Lower address
Memory transaction
1HCLK
data driven by FSMC
ADDSET ADDHLD (DATAST + 1)
HCLK cycles HCLK cycles HCLK cycles
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
ai15569
Doc ID 018909 Rev 3 1336/1416