RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS) 30.16.6 OTG_FS register map The table below gives the USB OTG register map and reset values. Table 175. OTG_FS register map and reset values Offset Register 31 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG_FS_GOT GCTL Reserved BSVLD ASVLD DBCT CIDSTS Reserved DHNPEN HSHNPEN HNPRQ HNGSCS Reserved SRQ Reset value 0 0 0 1 0 0 0 0 0 0 OTG_FS_GOT GINT Reserved DBCDNE ADTOCHG HNGDET Reserved HNSSCHG SRSSCHG Reserved Reset value 0 0 0 0 0 0 OTG_FS_GAH BCFG Reserved PTXFELVL TXFELVL Reserved Reset value 0 0 0 OTG_FS_GUS BCFG CTXPKT FDMOD FHMOD Reserved TRDT HNPCAP SRPCAP Reserved PHYSEL Reserved Doc ID 018909 Rev 3 1102/1416 SEDET SRQSCS Res. GINTMSK TOCAL Reset value 0 1 0 1 0 0 1 0 0 0 OTG_FS_GRST CTL AHBIDL Reserved TXFNUM RXFFLSH Reserved FCRST HSRST CSRST Reset value 1 0 0 0 0 0 0 0 0 0 0 OTG_FS_GINT STS WKUINT SRQINT DISCINT CIDSCHG Reserved PTXFE HCINT HPRTINT Reserved IPXFR/INCOMPISOOUT IISOIXFR OEPINT IEPINT Reserved EOPF ISOODRP ENUMDNE USBRST USBSUSP ESUSP Reserved GOUTNAKEFF GINAKEFF NPTXFE RXFLVL SOF OTGINT MMIS CMOD Reset value 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 OTG_FS_GINT MSK WUIM SRQIM DISCINT CIDSCHGM Reserved PTXFEM HCIM PRTIM Reserved IPXFRM/IISOOXFRM IISOIXFRM OEPINT IEPINT EPMISM Reserved EOPFM ISOODRPM ENUMDNEM USBRST USBSUSPM ESUSPM Reserved GONAKEFFM GINAKEFFM NPTXFEM RXFLVLM SOFM OTGINT MMISM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_GRXS TSR (host mode) Reserved PKTSTS DPID BCNT CHNUM Reset value OTG_FS_GRXS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSR (Device mode) Reserved FRMNUM PKTSTS DPID BCNT EPNUM Reset value OTG_FS_GRXS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSR (host mode) Reserved PKTSTS DPID BCNT CHNUM Reset value OTG_FS_GRXS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSPR (Device mode) Reserved FRMNUM PKTSTS DPID BCNT EPNUM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_GRXF SIZ Reserved RXFD Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reserved
USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong> 31 Table 175. OTG_FS register map and reset values (continued) Offset Register 0x028 0x02C 0x038 0x03C 0x100 0x104 0x108 0x10C OTG_FS_HNPT XFSIZ/ OTG_FS_DIEP TXF0 1103/1416 Doc ID 018909 Rev 3 NPTXFD/TX0FD NPTXFSA/TX0FSA Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_FS_HNPT XSTS NPTXQTOP NPTQXSAV NPTXFSAV Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Res. OTG_FS_ GCCFG Reserved NOVBUSSENS SOFOUTEN VBUSBSEN VBUSASEN Reserved .PWRDWN Reserved Reset value 0 0 0 0 0 OTG_FS_CID PRODUCT_ID Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 OTG_FS_HPTX FSIZ PTXFSIZ PTXSA Reset value 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 OTG_FS_DIEP TXF1 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 OTG_FS_DIEP TXF2 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 OTG_FS_DIEP TXF3 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0x400 OTG_FS_HCFG Reserved Reset value 0 0 0 0x404 OTG_FS_HFIR Reset value Reserved 1 1 1 0 1 0 1 FRIVL 0 0 1 1 0 0 0 0 0 0x408 OTG_FS_HFNU M FTREM FRNUM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x410 OTG_FS_HPTX STS PTXQTOP PTXQSAV PTXFSAVL Reset value 0 0 0 0 0 0 0 0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0x414 OTG_FS_HAIN T Reserved HAINT Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x418 OTG_FS_HAIN TMSK Reserved HAINTM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x440 OTG_FS_HPRT 0x500 0x520 0x540 Reserved PSPD PTCTL PPWR PLSTS Reserved PRST PSUSP PRES POCCHNG POCA FSLSS FSLSPCS PENCHNG PENA PCDET PCSTS Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCC HAR0 CHENA CHDIS ODDFRM DAD MCNT EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCC HAR1 CHENA CHDIS ODDFRM DAD MCNT EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCC HAR2 CHENA CHDIS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODDFRM DAD MCNT EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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Interrupts and events RM0090 Table
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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