RM0090: Reference manual - STMicroelectronics

Flexible static memory controller (FSMC) RM0090
Table 213. Programmable NAND/PC Card access parameters
Parameter Function Access mode Unit Min. Max.
Memory setup
time
Memory wait
Memory hold
Memory
databus high-Z
32.6.1 External memory interface signals
The following tables list the signals that are typically used to interface NAND Flash and PC
Card.
Note: Prefix “N”. specifies the associated signal as active low.
8-bit NAND Flash
Number of clock cycles (HCLK)
to set up the address before the
command assertion
t
Table 214. 8-bit NAND Flash
There is no theoretical capacity limitation as the FSMC can manage as many address
cycles as needed.
1351/1416 Doc ID 018909 Rev 3
Read/Write
Minimum duration (HCLK clock
cycles) of the command assertion Read/Write
Number of clock cycles (HCLK)
to hold the address (and the data
in case of a write access) after
the command de-assertion
Number of clock cycles (HCLK)
during which the databus is kept
in high-Z state after the start of a
write access
Read/Write
Write
FSMC signal name I/O Function
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
A[17] O NAND Flash address latch enable (ALE) signal
A[16] O NAND Flash command latch enable (CLE) signal
D[7:0] I/O 8-bit multiplexed, bidirectional address/data bus
NCE[x] O Chip select, x = 2, 3
NOE(= NRE) O Output enable (memory signal name: read enable, NRE)
NWE O Write enable
NWAIT/INT[3:2] I NAND Flash ready/busy input signal to the FSMC
1 256
2 256
1 255
0 255