RM0090: Reference manual - STMicroelectronics

USB on-the-go high-speed (OTG_HS) RM0090
Bit 17 NAKSTS: NAK status
Indicates the following:
0: The core is transmitting nonNAK handshakes based on the FIFO status.
1: The core is transmitting NAK handshakes on this endpoint.
When either the application or the core sets this bit, the core stops receiving data, even if
there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit’s
setting, the core always responds to SETUP data packets with an ACK handshake.
Bit 16 Reserved, must be kept at reset value.
Bit 15 USBAEP: USB active endpoint
This bit is always set to 1, indicating that a control endpoint 0 is always active in all
configurations and interfaces.
Bits 14:2 Reserved, must be kept at reset value.
Bits 1:0 MPSIZ: Maximum packet size
The maximum packet size for control OUT endpoint 0 is the same as what is programmed in
control IN endpoint 0.
00: 64 bytes
01: 32 bytes
10: 16 bytes
11: 8 bytes
OTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) (x = 1..3,
where x = Endpoint_number)
Address offset for OUT endpoints: 0xB00 + (Endpoint_number × 0x20)
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than
endpoint 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPENA
EPDIS
SODDFRM
SD0PID/SEVNFRM
SNAK
CNAK
rs rs w w w w
Reserved
1233/1416 Doc ID 018909 Rev 3
Stall
rw/
rs
SNPM
EPTYP
NAKSTS
EONUM/DPID
USBAEP
Reserved
MPSIZ
rw rw rw r r rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 EPENA: Endpoint enable
Applies to IN and OUT endpoints.
The application sets this bit to start transmitting data on an endpoint.
The core clears this bit before setting any of the following interrupts on this endpoint:
– SETUP phase done
– Endpoint disabled
– Transfer completed