RM0090: Reference manual - STMicroelectronics

RM0090 Hash processor (HASH)
HASH_HR6
Address offset: 0x328
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HASH_HR7
Address offset: 0x32C
Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these
registers assume their reset values.
22.4.6 HASH interrupt enable register (HASH_IMR)
Address offset: 0x20
Reset value: 0x0000 0000
H6
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H6
r r r r r r r r r r r r r r r r
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H7
r r r r r r r r r r r r r r r r
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Bits 31:2 Reserved, forced by hardware to 0.
Bit 1 DCIE: Digest calculation completion interrupt enable
0: Digest calculation completion interrupt disabled
1: Digest calculation completion interrupt enabled.
Bit 0 DINIE: Data input interrupt enable
0: Data input interrupt disabled
1: Data input interrupt enabled
DCIE DINIE
rw rw
Doc ID 018909 Rev 3 614/1416