RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Hash processor (HASH) 22.4.8 HASH context swap registers (HASH_CSRx) Address offset: 0x0F8 to 0x1C0 ● For HASH_CSR0 register: Reset value is 0x0000 0002. ● For others registers: Reset value is 0x0000 0000 , except for STM32F42x and STM32F43x devices where the HASH_CSR2 register reset value is 0x2000 0000 Additional registers are available from 0x1C1 to 0x1CC on STM32F42x and STM32F43x ● Reset value: 0x0000 0000. These registers contain the complete internal register states of the hash processor, and are useful when a context swap has to be done because a high-priority task has to use the hash processor while it is already in use by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved somewhere in the system memory space. Then the hash processor can be used by the preemptive task, and when hash computation is finished, the saved context can be read from memory and written back into these HASH_CSRx registers. HASH_CSRx Address offset: 0x0F8 to 0x1C0 on STM32F40x and STM32F41x Address offset: 0x0F8 to 0x1CC on STM32F42x and STM32F43x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CSx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Doc ID 018909 Rev 3 616/1416
Hash processor (HASH) <strong>RM0090</strong> 22.4.9 HASH register map Table 9 gives the summary HASH register map and reset values. Table 93. HASH register map and reset values on STM32F40x and STM32F41x Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0xF8 0x1C0 0x310 0x314 0x318 0x31C 0x320 Register name reset value HASH_CR 617/1416 Doc ID 018909 Rev 3 Register size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LKEY Reset value 0 0 0 0 0 0 0 0 0 0 0 0 HASH_DIN DATAIN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCAL HASH_STR Reserved NBLW Reset value 0 0 0 0 0 0 HASH_HR0 H0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR1 H1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR2 H2 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR3 H3 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR4 H4 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_IMR Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY HASH_SR Reserved Reset value 0 0 0 1 HASH_CSR0 CSR0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 HASH_CSR50 CSR50 ... ... Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved HASH_HR0 H0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR1 H1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR2 H2 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR3 H3 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR4 H4 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DINNE NBW ALGO[0] MODE Reserved DATATYPE DMAE INIT DMAS DCIS Reserved DCIE DINIE DINIS
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.4 DMA
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Window watchdog (WWDG) RM0090 19.6.
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
Page 1403 and 1404:
DMA_SxM1AR . . . . . . . . . . . .
Page 1405 and 1406:
HASH_SR . . . . . . . . . . . . . .
Page 1407 and 1408:
RNG_DR . . . . . . . . . . . . . .
Page 1409 and 1410:
Revision history RM0090 Revision hi
Page 1411 and 1412:
Revision history RM0090 Table 238.
Page 1413 and 1414:
Page 1415 and 1416:
show all

RM0090: Reference manual - STMicroelectronics

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