RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Serial peripheral interface (SPI) 27.5.3 SPI status register (SPI_SR) Address offset: 0x08 Reset value: 0x0002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits 15:9 Reserved. Forced to 0 by hardware. FRE BSY OVR MODF CRC ERR UDR CHSID E TXE RXNE r r r r rc_w0 r r r r Bit 8 FRE: Frame format error 0: No frame format error 1: A frame format error occurred This flag is set by hardware and cleared by software when the SPIx_SR register is read. Note: This flag is used when the SPI operates in TI slave mode or I2S slave mode (refer to Section 27.3.10). Bit 7 BSY: Busy flag 0: SPI (or I2S) not busy 1: SPI (or I2S) is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware. Note: BSY flag must be used with caution: refer to Section 27.3.7: Status flags and Section 27.3.8: Disabling the SPI. Bit 6 OVR: Overrun flag 0: No overrun occurred 1: Overrun occurred This flag is set by hardware and reset by a software sequence. Refer to Section 27.4.8 on page 831 for the software sequence. Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section 27.3.10 on page 814 for the software sequence. Note: Not used in I 2 S mode Bit 4 CRCERR: CRC error flag 0: CRC value received matches the SPI_RXCRCR value 1: CRC value received does not match the SPI_RXCRCR value This flag is set by hardware and cleared by software writing 0. Note: Not used in I 2 S mode Bit 3 UDR: Underrun flag 0: No underrun occurred 1: Underrun occurred This flag is set by hardware and reset by a software sequence. Refer to Section 27.4.8 on page 831 for the software sequence. Note: Not used in SPI mode Bit 2 CHSIDE: Channel side 0: Channel Left has to be transmitted or has been received 1: Channel Right has to be transmitted or has been received Note: Not used for SPI mode. No meaning in PCM mode Doc ID 018909 Rev 3 836/1416
Serial peripheral interface (SPI) <strong>RM0090</strong> Bit 1 TXE: Transmit buffer empty 0: Tx buffer not empty 1: Tx buffer empty Bit 0 RXNE: Receive buffer not empty 0: Rx buffer empty 1: Rx buffer not empty 27.5.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 27.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S mode) Address offset: 0x10 Reset value: 0x0007 DR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer). A write to the data register will write into the Tx buffer and a read from the data register will return the value held in the Rx buffer. Notes for the SPI mode: Depending on the data frame format selection bit (DFF in SPI_CR1 register), the data sent or received is either 8-bit or 16-bit. This selection has to be made before enabling the SPI to ensure correct operation. For an 8-bit data frame, the buffers are 8-bit and only the LSB of the register (SPI_DR[7:0]) is used for transmission/reception. When in reception mode, the MSB of the register (SPI_DR[15:8]) is forced to 0. For a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is used for transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRCPOLY[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CRCPOLY[15:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. Note: Not used for the I 2 S mode. 837/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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