RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS) 31 Table 182. OTG_HS register map and reset values (continued) Offset Register 0x100 0x104 0x108 0x10C 0x110 0x400 OTG_HS_HPTX FSIZ PTXFD PTXSA Reset value 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 OTG_HS_DIEP TXF1 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP TXF2 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP TXF3 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP TXF4 INEPTXFD INEPTXSA Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCF G Reserved Reset value 0 0 0 0x404 OTG_HS_HFIR Reset value Reserved 1 1 1 0 1 0 1 FRIVL 0 0 1 1 0 0 0 0 0 0x408 OTG_HS_HFN UM FTREM FRNUM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x410 OTG_HS_HPTX STS PTXQTOP PTXQSAV PTXFSAVL Reset value 0 0 0 0 0 0 0 0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0x414 OTG_HS_HAIN T Reserved HAINT Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x418 OTG_HS_HAIN TMSK Reserved HAINTM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x440 OTG_HS_HPRT 0x500 0x520 0x540 0x560 0x580 0x5A0 Reserved PSPD PTCTL Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR0 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR PPWR Doc ID 018909 Rev 3 1246/1416 PLSTS Reserved PRST PSUSP PRES POCCHNG POCA EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR1 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR2 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR3 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR4 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR5 CHENA CHDIS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSLSS PENCHNG PENA FSLSPCS PCDET PCSTS
USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong> 31 Table 182. OTG_HS register map and reset values (continued) Offset Register 0x5C0 0x5E0 0x600 0x620 0x640 0x660 0x504 0x508 0x524 0x528 0x544 0x548 0x564 OTG_HS_HCC HAR6 CHENA CHDIS ODDFRM DAD MC 1247/1416 Doc ID 018909 Rev 3 EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR7 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR8 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR9 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR10 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCC HAR11 CHENA CHDIS ODDFRM DAD MC EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT0 SPLITEN Reserved COMPLSPLT XACTPOS HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T0 Reserved DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PL1 SPLITEN Reserved COMPLSPLT XACTPOS HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T1 Reserved DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT2 SPLITEN Reserved COMPLSPLT XACTPOS HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T2 Reserved DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT3 SPLITEN 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved COMPLSPLT XACTPOS HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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Interrupts and events RM0090 Table
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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