RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS) Table 182. OTG_HS register map and reset values (continued) Offset Register 31 0x828 0x82C 0x830 0x834 0x838 0x83C 0x844 0x884 0x900 0x918 0x920 0x938 0x940 0x958 OTG_HS_DVB USDIS Reserved VBUSDT Reset value 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 OTG_HS_DVB USPULSE Reserved DVBUSP Reset value 0 1 0 1 1 0 1 1 1 0 0 0 OTG_HS_DTH RCTL Reserved ARPEN Reserved RXTHRLEN RXTHREN Reserved TXTHRLEN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP EMPMSK Reserved INEPTXFEM Reset value OTG_HS_DEA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHINT Reserved Reserved Reset value 0 0 OTG_HS_DEA CHINTMSK Reserved Reserved Reset value 0 0 OTG_HS_DIEP EACHMSK1 Reserved NAKM Reserved BIM Reset value 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PEACHMSK1 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP CTL0 EPENA EPDIS SODDFRM SD0PID/SEVNFRM SNAK CNAK TXFNUM STALL Reserved EPTYP NAKSTS EONUM/DPID USBAEP NYETM NAKM BERRM Reserved Doc ID 018909 Rev 3 1252/1416 Reserved BIM TXFURM TXFURM Reserved INEPNEM Reserved INEPNEM INEPNMM ITTXFEMSK INEPNMM ITTXFEMSK MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TG_FS_DTXFS TS0 Reserved INEPTFSAV Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP CTL1 EPENA EPDIS SODDFRM SD0PID/SEVNFRM SNAK CNAK TXFNUM Stall Reserved EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TG_FS_DTXFS TS1 Reserved INEPTFSAV Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP CTL2 EPENA EPDIS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SODDFRM SD0PID/SEVNFRM SNAK CNAK TXFNUM Stall Reserved EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TG_FS_DTXFS TS2 Reserved INEPTFSAV Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 TOM TOM ISOTHREN Reserved EPDM Reserved EPDM NONISOTHREN Reserved Reserved XFRCM XFRCM
USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong> Table 182. OTG_HS register map and reset values (continued) Offset Register 31 0x960 0x978 0x980 0x9A0 0x9C0 0x9E0 0xB00 0xB20 0xB40 OTG_HS_DIEP CTL3 EPENA EPDIS SODDFRM SD0PID/SEVNFRM SNAK 1253/1416 Doc ID 018909 Rev 3 CNAK TXFNUM Stall Reserved EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TG_FS_DTXFS TS3 Reserved INEPTFSAV Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP CTL4 EPENA EPDIS SODDFRM SD0PID/SEVNFRM SNAK CNAK TXFNUM Stall Reserved EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP CTL5 EPENA EPDIS SODDFRM SD0PID/SEVNFRM SNAK CNAK TXFNUM STALL Reserved EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP CTL6 EPENA EPDIS SODDFRM SD0PID/SEVNFRM SNAK CNAK TXFNUM STALL Reserved EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP CTL7 EPENA EPDIS SODDFRM SD0PID/SEVNFRM SNAK CNAK TXFNUM STALL Reserved EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PCTL0 EPENA EPDIS Reserved SNAK CNAK Reserved STALL SNPM EPTY P NAKSTS Reserved USBAEP Reserved Reset value 0 0 0 0 0 0 0 0 0 1 0 0 OTG_HS_DOE PCTL1 EPENA EPDIS SODDFRM SD0PID/SEVNFRM SNAK CNAK Reserved STALL SNPM EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PCTL2 EPENA EPDIS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SODDFRM SD0PID/SEVNFRM SNAK CNAK Reserved Stall SNPM EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSI Z
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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