RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31.12.6 OTG_HS register map Reserved Bit 31:5 Reserved, must be kept at reset value. The table below gives the USB OTG register map and reset values. Doc ID 018909 Rev 3 1244/1416 PHYSUSP Reserved GATEHCLK STPPCLK rw rw rw Bit 4 PHYSUSP: PHY suspended Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended after the application has set the STPPCLK bit (bit 0). Bits 3:2 Reserved, must be kept at reset value. Bit 1 GATEHCLK: Gate HCLK The application sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. Bit 0 STPPCLK: Stop PHY clock The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. 31 Table 182. OTG_HS register map and reset values Offset Register 0x000 0x004 0x008 0x00C 0x010 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG_HS_GOT GCTL Reserved BSVLD ASVLD DBCT CIDSTS Reserved DHNPEN HSHNPEN HNPRQ HNGSCS Reserved SRQ Reset value 0 0 0 1 0 0 0 0 0 0 OTG_HS_GOT GINT Reserved DBCDNE ADTOCHG HNGDET Reserved HNSSCHG SRSSCHG Reserved Reset value 0 0 0 0 0 0 OTG_HS_GAH BCFG Reserved PTXFELVL TXFELVL SEDET SRQSCS Res. Reserved GINT Reset value 0 0 0 OTG_HS_GUS BCFG CTXPKT FDMOD FHMOD Reserved ULPIIPD PTCI PCCI TSDPS ULPIEVBUSI ULPIEVBUSD ULPICSM ULPIAR ULPIFSLS Reserved PHYLPCS Reserved TRDT HNPCAP SRPCAP Reserved PHSEL Reserved TOCAL Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 OTG_HS_GRS TCTL AHBIDL DMAREQ Reserved TXFNUM TXFFLSH RXFFLSH Reserved FCRST HSRST CSRST Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0
USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong> 31 Table 182. OTG_HS register map and reset values (continued) Offset Register 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x038 0x03C OTG_HS_GINT STS WKUINT SRQINT DISCINT CIDSCHG Reserved PTXFE 1245/1416 Doc ID 018909 Rev 3 HCINT HPRTINT Reserved DATAFSUSP IPXFR/INCOMPISOOUT IISOIXFR OEPINT IEPINT Reset value 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_GINT MSK WUIM SRQIM DISCINT CIDSCHGM Reserved PTXFEM HCIM PRTIM Reserved FSUSPM IPXFRM/IISOOXFRM IISOIXFRM OEPINT IEPINT EPMISM Reserved EOPF ISOODRP ENUMDNE Reserved EOPFM ISOODRPM ENUMDNEM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_GRX STSR (Host mode) Reserved USBRST USBSUSP USBRST ESUSP USBSUSPM ESUSPM Reserved Reserved BOUTNAKEFF GINAKEFF GONAKEFFM GINAKEFFM NPTXFE RXFLVL NPTXFEM RXFLVLM SOF SOFM OTGINT OTGINT MMIS PKTSTS DPID BCNT CHNUM Reset value OTG_HS_GRX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STSR (peripheral mode) Reserved FRMNUM PKTSTS DPID BCNT EPNUM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_GRX STSP (Host mode) Reserved PKTSTS DPID BCNT CHNUM Reset value OTG_HS_GRX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STSP (peripheral mode) Reserved FRMNUM PKTSTS DPID BCNT EPNUM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_GRX FSIZ Reserved RXFD Reset value OTG_HS_GNP 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 TXFSIZ (Host mode) NPTXFD NPTXFSA Reset value OTG_HS_GNP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 TXFSIZ (peripheral mode) TX0FD TX0FSA Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_HS_GNP TXSTS NPTXQTOP NPTQXSAV NPTXFSAV Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_HS_GI2C CTL Res. BSYDNE RW 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I2CDATSE0 I2CDEVADR Reserved ACK Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_GCC FG Reserved I2CEN NOVBUSSENS SOFOUTEN ADDR REGADDR RWDATA VBUSBSEN VBUSASEN .I2CPADEN .PWRDWN Reset value 0 0 0 0 0 0 Reserved OTG_HS_CID PRODUCT_ID Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 MMISM CMOD Reserved
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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