RM0090: Reference manual - STMicroelectronics

DMA controller (DMA) RM0090
Figure 26. System implementation of the two DMA controllers (STM32F42x and STM32F43x)
To AHB2
peripherals
To AHB2
peripherals
AHB slave
AHB slave
DMA controller 2
DMA request
MAPPING
DMA controller 1 AHB periph
1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus
only DMA2 streams are able to perform memory-to-memory transfers.
9.3.2 DMA transactions
A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are softwareprogrammable.
Each DMA transfer consists of three operations:
● A loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
● A storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
● A post-decrement of the DMA_SxNDTR register, which contains the number of
transactions that still have to be performed
215/1416 Doc ID 018909 Rev 3
Arbiter
Arbiter
FIFO
FIFO
AHB memory
port
AHB periph
port
AHB memory
port
port
Bus Matrix
(AHB multilayer)
DCODE
ICODE
AHB-APB
bridge2
(dual AHB)
AHB-APB
bridge1
(dual AHB)
Flash
memory
112 KB SRAM
16 KB SRAM
64 KB SRAM
AHB1 peripherals
APB1
APB2
AHB2 peripherals
External memory
controller (FSMC)
APB2
peripherals
APB1
peripherals
MS30437V1