RM0090: Reference manual - STMicroelectronics

Contents RM0090
12.4.2 Independent trigger with single LFSR generation . . . . . . . . . . . . . . . . 314
12.4.3 Independent trigger with different LFSR generation . . . . . . . . . . . . . . 314
12.4.4 Independent trigger with single triangle generation . . . . . . . . . . . . . . . 314
12.4.5 Independent trigger with different triangle generation . . . . . . . . . . . . . 315
12.4.6 Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
12.4.7 Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 315
12.4.8 Simultaneous trigger with single LFSR generation . . . . . . . . . . . . . . . 316
12.4.9 Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 316
12.4.10 Simultaneous trigger with single triangle generation . . . . . . . . . . . . . . 316
12.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 317
12.5 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
12.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
12.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 320
12.5.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
12.5.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
12.5.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
12.5.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
12.5.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
12.5.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
12.5.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
12.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
12.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
12.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 324
12.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 324
12.5.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
12.5.15 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
13 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
13.1 DCMI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
13.2 DCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
11/1416 Doc ID 018909 Rev 3