RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> List of tables Table 49. External trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Table 50. External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Table 51. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Table 52. ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Table 53. ADC register map and reset values for each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Table 54. ADC register map and reset values (common ADC registers) . . . . . . . . . . . . . . . . . . . . . 305 Table 55. DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Table 56. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Table 57. DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Table 58. DCMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Table 59. DCMI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Table 60. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . . 329 Table 61. Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . . 329 Table 62. Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . . 329 Table 63. Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . . 330 Table 64. Data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Table 65. Data storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Table 66. Data storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Table 67. DCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Table 68. DCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Table 69. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Table 70. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Table 71. Output control bits for complementary OCx and OCxN channels with break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Table 72. TIM1&TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Table 73. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Table 74. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 Table 75. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 Table 76. TIM2 to TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 Table 77. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Table 78. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 Table 79. TIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 Table 80. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Table 81. TIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 Table 82. TIM6&TIM7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Table 83. Min/max IWDG timeout period at 32 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Table 84. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 Table 85. Timeout values at 30 MHz (f PCLK1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Table 86. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Table 87. Number of cycles required to process each 128-bit block (STM32F40x and STM32F41x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544 Table 88. Number of cycles required to process each 128-bit block (STM32F42x and STM32F43x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544 Table 89. Data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 Table 90. CRYP register map and reset values for STM32F40x and STM32F41x . . . . . . . . . . . . . 586 Table 91. CRYP register map and reset values for STM32F42x and STM32F43x . . . . . . . . . . . . . 587 Table 92. RNG register map and reset map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Table 93. HASH register map and reset values on STM32F40x and STM32F41x . . . . . . . . . . . . . 617 Table 94. HASH register map and reset values on STM32F42x and STM32F43x . . . . . . . . . . . . . 618 Table 95. Effect of low power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 Table 96. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 Table 97. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 Doc ID 018909 Rev 3 34/1416
List of tables <strong>RM0090</strong> Table 98. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 Table 99. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 Table 100. bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 Table 101. Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . . . . . . . . . . . . . . . . . . 716 Table 102. SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 Table 103. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 Table 104. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Table 105. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Table 106. Error calculation for programmed baud rates at f PCLK = 8 MHz or f PCLK = 12 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 Table 107. Error calculation for programmed baud rates at f PCLK = 8 MHz or f PCLK =12 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 Table 108. Error calculation for programmed baud rates at f PCLK = 16 MHz or f PCLK = 24 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Table 109. Error calculation for programmed baud rates at f PCLK = 16 MHz or f PCLK = 24 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Table 110. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Table 111. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 Table 112. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 Table 113. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 Table 114. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 Table 115. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz, oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 Table 116. USART receiver’s tolerance when DIV fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 Table 117. USART receiver’s tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . 761 Table 118. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 Table 119. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 Table 120. USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 Table 121. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 Table 122. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 Table 123. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) . . . . . . . . . . . . . . . . . . . . 826 Table 124. I 2 S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 Table 125. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 Table 126. SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 Table 127. Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 Table 128. Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 Table 129. Long response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 Table 130. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 Table 131. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 Table 132. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 Table 133. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 Table 134. Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 Table 135. SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 Table 136. Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 Table 137. Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 Table 138. AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 Table 139. Maximum AU size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 35/1416 Doc ID 018909 Rev 3
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.5.5 D
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 Fig
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 The fo
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Real-time clock (RTC) RM0090 Sectio
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Real-time clock (RTC) RM0090 23.6 R
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Real-time clock (RTC) RM0090 Bit 3
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Controller area network (bxCAN) RM0
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Universal synchronous asynchronous
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Serial peripheral interface (SPI) R
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Ethernet (ETH): media access contro
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USB on-the-go full-speed (OTG_FS) R
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USB on-the-go high-speed (OTG_HS) R
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Flexible static memory controller (
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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