RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Secure digital input/output interface (SDIO) Bit 6 CMDRENDIE: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0: Command response received interrupt disabled 1: command Response Received interrupt enabled Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 0: Rx FIFO overrun error interrupt disabled 1: Rx FIFO overrun error interrupt enabled Bit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 0: Tx FIFO underrun error interrupt disabled 1: Tx FIFO underrun error interrupt enabled Bit 3 DTIMEOUTIE: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 0: Data timeout interrupt disabled 1: Data timeout interrupt enabled Bit 2 CTIMEOUTIE: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 0: Command timeout interrupt disabled 1: Command timeout interrupt enabled Bit 1 DCRCFAILIE: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 0: Data CRC fail interrupt disabled 1: Data CRC fail interrupt enabled Bit 0 CCRCFAILIE: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0: Command CRC fail interrupt disabled 1: Command CRC fail interrupt enabled 28.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) Address offset: 0x48 Reset value: 0x0000 0000 The SDIO_FIFOCNT register contains the remaining number of words to be written to or read from the FIFO. The FIFO counter loads the value from the data length register (see SDIO_DLEN) when the data transfer enable bit, DTEN, is set in the data control register (SDIO_DCTRL register) and the DPSM is at the Idle state. If the data length is not wordaligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFOCOUNT r r r r r r r r r r r r r r r r r r r r r r r r Bits 31:24 Reserved, must be kept at reset value Bits 23:0 FIFOCOUNT: Remaining number of words to be written to or read from the FIFO. Doc ID 018909 Rev 3 896/1416
Secure digital input/output interface (SDIO) <strong>RM0090</strong> 28.9.15 SDIO data FIFO register (SDIO_FIFO) Address offset: 0x80 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 28.9.16 SDIO register map FIF0Data rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 FIFOData: Receive and transmit FIFO data The FIFO data occupies 32 entries of 32-bit words, from address: SDIO base + 0x080 to SDIO base + 0xFC. The following table summarizes the SDIO registers. 31 Table 157. SDIO register map Offset Register 0x00 SDIO_POWER 0x04 SDIO_CLKCR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x08 SDIO_ARG CMDARG 0x0C SDIO_CMD 0x10 SDIO_RESPCM D 897/1416 Doc ID 018909 Rev 3 Reserved Reserved Reserved HWFC_EN NEGEDGE CE-ATACMD nIEN WIDBUS ENCMDcompl SDIOSuspend BYPASS PWRSAV CLKEN CPSMEN WAITPEND WAITINT Reserved RESPCMD 0x14 SDIO_RESP1 CARDSTATUS1 0x18 SDIO_RESP2 CARDSTATUS2 0x1C SDIO_RESP3 CARDSTATUS3 0x20 SDIO_RESP4 CARDSTATUS4 0x24 SDIO_DTIMER DATATIME 0x28 SDIO_DLEN Reserved DATALENGTH 0x2C SDIO_DCTRL 0x30 SDIO_DCOUNT Reserved DATACOUNT 0x34 SDIO_STA Reserved CEATAEND SDIOIT Reserved RXDAVL TXDAVL RXFIFOE TXFIFOE RXFIFOF TXFIFOF RXFIFOHF TXFIFOHE RXACT TXACT SDIOEN RWMOD CMDACT DBCKEND RWSTOP RWSTART STBITERR DATAEND WAITRESP CMDSENT CMDREND DBLOCKSIZE RXOVERR TXUNDERR CLKDIV CMDINDEX DMAEN DTMODE DTIMEOUT CTIMEOUT PWRCTRL DTDIR DTEN DCRCFAIL CCRCFAIL
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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