RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> DMA controller (DMA) 9.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) Address offset: 0x24 + 0x24 × stream number Reset value: 0x0000 0021 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits 31:8 Reserved, must be kept at reset value. Bits 7 FEIE: FIFO error interrupt enable This bit is set and cleared by software. 0: FE interrupt disabled 1: FE interrupt enabled Bits 6 Reserved, must be kept at reset value. FEIE Reser FS[2:0] DMDIS FTH[1:0] rw ved r r r rw rw rw Bits 5:3 FS[2:0]: FIFO status These bits are read-only. 000: 0 < fifo_level < 1/4 001: 1/4 ≤ fifo_level < 1/2 010: 1/2 ≤ fifo_level < 3/4 011: 3/4 ≤ fifo_level < full 100: FIFO is empty 101: FIFO is full others: no meaning These bits are not relevant in the direct mode (DMDIS bit is zero). Bits 2 DMDIS: Direct mode disable This bit is set and cleared by software. It can be set by hardware. 0: Direct mode enabled 1: Direct mode disabled This bit is protected and can be written only if EN is ‘0’. This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’ because the direct mode is not allowed in the memory-to-memory configuration. Bits 1:0 FTH[1:0]: FIFO threshold selection These bits are set and cleared by software. 00: 1/4 full FIFO 01: 1/2 full FIFO 10: 3/4 full FIFO 11: full FIFO These bits are not used in the direct mode when the DMIS value is zero. These bits are protected and can be written only if EN is ‘1’. Doc ID 018909 Rev 3 242/1416
DMA controller (DMA) <strong>RM0090</strong> 9.5.11 DMA register map Table 42 summarizes the DMA registers. Table 42. DMA register map and reset values Offset Register 0x0000 0x0004 0x0008 0x000C 0x0010 DMA_LISR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TCIF3 HTIF3 TEIF3 DMEIF3 Reserved FEIF3 TCIF2 HTIF2 TEIF2 243/1416 Doc ID 018909 Rev 3 DMEIF2 Reserved FEIF2 Reserved TCIF1 HTIF1 TEIF1 DMEIF1 Reserved FEIF1 TCIF0 HTIF0 TEIF0 DMEIF0 Reserved FEIF0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_HISR Reserved TCIF7 HTIF7 TEIF7 DMEIF7 Reserved FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Reserved FEIF6 Reserved TCIF5 HTIF5 TEIF5 DMEIF5 Reserved FEIF5 TCIF4 HTIF4 TEIF4 DMEIF4 Reserved FEIF4 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_LIFCR Reserved CTCIF3 CHTIF3 TEIF3 CDMEIF3 Reserved CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 Reserved CFEIF2 Reserved CTCIF1 CHTIF1 CTEIF1 CDMEIF1 Reserved CFEIF1 CTCIF0 CHTIF0 CTEIF0 CDMEIF0 Reserved CFEIF0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_HIFCR Reserved CTCIF7 CHTIF7 CTEIF7 CDMEIF7 Reserved CFEIF7 CTCIF6 CHTIF6 CTEIF6 CDMEIF6 Reserved CFEIF6 Reserved CTCIF5 CHTIF5 CTEIF5 CDMEIF5 Reserved CFEIF5 CTCIF4 CHTIF4 CTEIF4 CDMEIF4 Reserved CFEIF4 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S0CR Reserved CHSEL[2:0] MBURST[1:0] PBURST[1:0] Reserved CT DBM PL[1:0] PINCOS MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR[1:0] PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0014 DMA_S0NDTR Reset value Reserved 0 0 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0x0018 0x001C 0x0020 0x0024 0x0028 DMA_S0PAR PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S0M0AR M0A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S0M1AR M1A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S0FCR Reserved FEIE Reserved FS[2:0] Reset value 0 1 0 0 0 0 1 DMA_S1CR Reserved CHSEL [2:0] MBURST[1:] PBURST[1:0] ACK CT DBM PL[1:0] PINCOS MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR[1:0] DMDIS FTH [1:0] PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x002C DMA_S1NDTR Reset value Reserved 0 0 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0x0030 DMA_S1PAR PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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General-purpose I/Os (GPIO) RM0090
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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show all

RM0090: Reference manual - STMicroelectronics

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