RM0090: Reference manual - STMicroelectronics

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RM0090 Reset and clock control for (RCC) Figure 13. Clock tree OSC32_IN OSC32_OUT PHY Ethernet 25 to 50 MHz MCO2 MCO1 OSC_OUT OSC_IN I2S_CKIN USB2.0 PHY 24 to 60 MHz LSE OSC 32.768 kHz PLL /1 to 5 /1 to 5 4-26 MHz HSE OSC VCO xN VCO xN PLLI2S / P / Q / R / P / Q / R ETH_MII_TX_CLK_MII ETH_MII_RX_ CLK_MII OTG_HS_SCL LSI RC 32 kHz SYSCLK LSE 16 MHz HSI RC HSE / M PLL48CK PLLI2SCLK Ext. clock LSI HSI I2SSRC LSE /2 to 31 Watchdog enable RTCSEL[1:0] PLLCLK /2,20 MII_RMII_SEL in SYSCFG_PMC IWDGCLK RTCCLK AHB PRESC / 1,2,..512 to independent watchdog APBx PRESC / 1,2,4,8,16 Peripheral clock enable Peripheral if (APBx presc = 1x1 else x2 Ethernet PTP clock APBx peripheral clocks APBx timer clocks 48 MHz clocks USBHS ULPI clock ai16088c 1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet. HSI HSE RTC enable HSE_RTC Peripheral clock enable Peripheral clock enable Peripheral clock enable SW SYSCLK 168 MHz max to RTC MACTXCLK to Ethernet MAC MACRXCLK Peripheral clock enable MACRMIICLK 168 MHz max. Clock Enable /8 clock enable Peripheral clock enable Peripheral clock enable Peripheral clock enable HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free-running clock I2S clocks Doc ID 018909 Rev 3 114/1416
Reset and clock control for (RCC) RM0090 The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like Ethernet, USB OTG FS and HS, I2S and SDIO. Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is 168 MHz. The maximum allowed frequency of the high-speed APB2 domain is 84 MHz. The maximum allowed frequency of the low-speed APB1 domain is 42 MHz All peripheral clocks are derived from the system clock (SYSCLK) except for: ● The USB OTG FS clock (48 MHz), the random analog generator (RNG) clock (≤ 48 MHz) and the SDIO clock (≤ 48 MHz) which are coming from a specific output of PLL (PLL48CLK) ● The I2S clock To achieve high-quality audio performance, the I2S clock can be derived either from a specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For more information about I2S clock frequency and precision, refer to Section 27.4.4: Clock generator. ● The USB OTG HS (60 MHz) clock which is provided from the external PHY ● The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external PHY. For further information on the Ethernet configuration, please refer to Section 29.4.4: MII/RMII selection in the Ethernet peripheral description. When the Ethernet is used, the AHB clock frequency must be at least 25 MHz. The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock (HCLK), configurable in the SysTick control and status register. The timer clock frequencies for STM32F40x and STM32F41x are automatically set by hardware. There are two cases: 1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected. The timer clock frequencies for STM32F42x and STM32F43x are automatically set by hardware. There are two cases depending on the value of TIMPRE bit in RCC_CFGR register: ● If TIMPRE bit in RCC_DKCFGR register is reset: If the APB prescaler is configured to a division factor of 1, the timer clock frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies are twice the frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx. ● If TIMPRE bit in RCC_DKCFGR register is set: If the APB prescaler is configured to a division factor of 1 or 2, the timer clock frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four times the frequency of the APB domain to which the timers are connected: TIMxCLK = 4xPCLKx. FCLK acts as Cortex-M4F free-running clock. For more details, refer to the Cortex-M4F technical reference manual. 115/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 RTC_TR
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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