RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Debug support (DBG) The core does not allow FCLK or HCLK to be turned off during a debug session. As these are required for the debugger connection, during a debug, they must remain active. The MCU integrates special means to allow the user to debug software in low-power modes. For this, the debugger host must first set some debug configuration registers to change the low-power mode behavior: ● In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by the debugger. This will feed HCLK with the same clock that is provided to FCLK (system clock previously configured by the software). ● In Stop mode, the bit DBG_STOP must be previously set by the debugger. This will enable the internal RC oscillator clock to feed FCLK and HCLK in STOP mode. 33.16.2 Debug support for timers, watchdog, bxCAN and I 2 C During a breakpoint, it is necessary to choose how the counter of timers and watchdog should behave: ● They can continue to count inside a breakpoint. This is usually required when a PWM is controlling a motor, for example. ● They can stop to count inside a breakpoint. This is required for watchdog purposes. For the bxCAN, the user can choose to block the update of the receive register during a breakpoint. For the I 2 C, the user can choose to block the SMBUS timeout during a breakpoint. 33.16.3 Debug MCU configuration register This register allows the configuration of the MCU under DEBUG. This concerns: ● Low-power mode support ● Timer and watchdog counter support ● bxCAN communication support ● Trace pin assignment This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004 It is asynchronously reset by the PORESET (and not the system reset). It can be written by the debugger under system reset. If the debugger host does not support these features, it is still possible for the user software to write to these registers. DBGMCU_CR Address: 0xE004 2004 Only 32-bit access supported POR Reset: 0x0000 0000 (not reset by system reset) Doc ID 018909 Rev 3 1388/1416
Debug support (DBG) <strong>RM0090</strong> 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits 31:8 Reserved, must be kept at reset value. TRACE_ MODE [1:0] 1389/1416 Doc ID 018909 Rev 3 TRACE _ IOEN Reserved DBG_ STAND BY DBG_ STOP DBG_ SLEEP rw rw rw rw rw rw Bits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control – With TRACE_IOEN=0: TRACE_MODE=xx: TRACE pins not assigned (default state) – With TRACE_IOEN=1: – TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode – TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 – TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 – TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 Bits 4:3 Reserved, must be kept at reset value. Bit 2 DBG_STANDBY: Debug Standby mode 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. From software point of view, exiting from Standby is identical than fetching reset vector (except a few status bit indicated that the MCU is resuming from Standby) 1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU generate a system reset during Standby mode so that exiting from Standby is identical than fetching from reset Bit 1 DBG_STOP: Debug Stop mode 0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently, the software must reprogram the clock controller to enable the PLL, the Xtal, etc. 1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are provided by the internal RC oscillator which remains active in STOP mode. When exiting STOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal, etc. (in the same way it would do in case of DBG_STOP=0) Bit 0 DBG_SLEEP: Debug Sleep mode 0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled. In Sleep mode, the clock controller configuration is not reset and remains in the previously programmed state. Consequently, when exiting from Sleep mode, the software does not need to reconfigure the clock controller. 1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same clock that is provided to FCLK (system clock as previously configured by the software).
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 10.3 E
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Page 1393 and 1394: Debug support (DBG) RM0090 33.17.2
Page 1399 and 1400: Device electronic signature RM0090
Page 1401 and 1402: A ADC_CCR . . . . . . . . . . . . .
Page 1403 and 1404: DMA_SxM1AR . . . . . . . . . . . .
Page 1405 and 1406: HASH_SR . . . . . . . . . . . . . .
Page 1407 and 1408: RNG_DR . . . . . . . . . . . . . .
Page 1409 and 1410: Revision history RM0090 Revision hi
Page 1411 and 1412: Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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