RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> T TIM2_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . .475 TIM5_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . .476 TIMx_ARR . . . . . . . . . . . . . . . . . . . . . . . . . . 470, 509, 518, 530 TIMx_BDTR . . . . . . . . . . . . . . . . . . . . . . . . . .412 TIMx_CCER . . . . . . . . . . . . . . . . . . . . . . . . . 405, 468, 508, 517 TIMx_CCMR1 . . . . . . . . . . . . . . . . . . . . . . . 401, 464, 505, 515 TIMx_CCMR2 . . . . . . . . . . . . . . . . . . . . . . . 404, 467 TIMx_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . . 410, 471, 510, 519 TIMx_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . . 411, 471, 510 TIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . . . . . 411, 472 TIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . . . . . 412, 472 TIMx_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . 409, 470, 509, 518, 529 TIMx_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 390, 455, 498, 512, 527 TIMx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 391, 457, 499, 528 TIMx_DCR . . . . . . . . . . . . . . . . . . . . . . . . . . 414, 473 TIMx_DIER . . . . . . . . . . . . . . . . . . . . . . . . . . 396, 460, 502, 528 TIMx_DMAR . . . . . . . . . . . . . . . . . . . . . . . . . 415, 473 TIMx_EGR . . . . . . . . . . . . . . . . . . . . . . . . . . 399, 463, 504, 513, 529 TIMx_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . 409, 470, 509, 518, 530 TIMx_RCR . . . . . . . . . . . . . . . . . . . . . . . . . . .410 TIMx_SMCR . . . . . . . . . . . . . . . . . . . . . . . . . 394, 458, 500 TIMx_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 398, 461, 503, 512, 529 U USART_BRR . . . . . . . . . . . . . . . . . . . . . . . . .781 USART_CR1 . . . . . . . . . . . . . . . . . . . . . . . . .781 USART_CR2 . . . . . . . . . . . . . . . . . . . . . . . . .784 USART_CR3 . . . . . . . . . . . . . . . . . . . . . . . . .785 USART_DR . . . . . . . . . . . . . . . . . . . . . . . . . .780 USART_GTPR . . . . . . . . . . . . . . . . . . . . . . . .788 USART_SR . . . . . . . . . . . . . . . . . . . . . . . . . .778 W WWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .542 WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .541 WWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .542 Doc ID 018909 Rev 3 1408/1416
Revision history <strong>RM0090</strong> Revision history Table 238. Document revision history Date Version Changes 15-Sep-2011 1 Initial release. 19-Oct-2012 2 1409/1416 Doc ID 018909 Rev 3 Updated reference documents and added Table 1: Applicable products on cover page. MEMORY: Updated Section 2.3.1: Embedded SRAM. PWR: Updated VDDA and VREF+ decoupling capacitor in Figure 7: Power supply overview. Updated case of no external battery in Section 5.1.2: Battery backup domain. VOSRDY bit changed to read-only in Section 5.4.3: PWR power control/status register (PWR_CSR). Removed VDDA in Section 5.2.3: Programmable voltage detector (PVD) and remove VDDA in PVDO bit description (Section 5.4.3: PWR power control/status register (PWR_CSR)). RCC: Updated Figure 12: Simplified diagram of the reset circuit and minimum reset pulse duration guaranteed by pulse generator restricted to internal reset sources. GPIOs: Updated Section 7.3.1: General-purpose I/O (GPIO). DMA: Updated direct mode description in Section 9.2: DMA main features. Updated direct mode description in Section : Memory-to-peripheral mode, and Section 9.3.12: FIFO/Direct mode. Modified Stream2 /Channel 2 in Table 33: DMA1 request mapping. Added note related to EN bit in Section 9.5.5: DMA stream x configuration register (DMA_SxCR) (x = 0..7). Updated definition of NDT[15:0] bits in Section 9.5.6: DMA stream x number of data register (DMA_SxNDTR) (x = 0..7). Updated register access in Section 9.5: DMA registers. Interrupts: Updated number of maskable interrupts to 82 in Section 10.1.1: NVIC featuress. EXTI: Updated Section 10.2: External interrupt/event controller (EXTI)
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 RTC_TR
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Page 1327 and 1328:
Page 1329 and 1330:
Page 1331 and 1332:
Page 1333 and 1334:
Page 1335 and 1336:
Page 1337 and 1338:
Page 1339 and 1340:
Page 1341 and 1342:
Page 1343 and 1344:
Page 1345 and 1346:
Page 1347 and 1348:
Page 1349 and 1350:
Page 1351 and 1352:
Page 1353 and 1354:
Page 1355 and 1356:
Page 1357 and 1358: Flexible static memory controller (
Page 1367 and 1368: Debug support (DBG) RM0090 33 Debug
Page 1369 and 1370: Debug support (DBG) RM0090 Figure 4
Page 1371 and 1372: Debug support (DBG) RM0090 33.4.3 I
Page 1373 and 1374: Debug support (DBG) RM0090 Figure 4
Page 1375 and 1376: Debug support (DBG) RM0090 Only the
Page 1377 and 1378: Debug support (DBG) RM0090 Table 22
Page 1379 and 1380: Debug support (DBG) RM0090 Note: No
Page 1381 and 1382: Debug support (DBG) RM0090 33.9 AHB
Page 1383 and 1384: Debug support (DBG) RM0090 33.11 Ca
Page 1385 and 1386: Debug support (DBG) RM0090 For this
Page 1387 and 1388: Debug support (DBG) RM0090 33.15.3
Page 1389 and 1390: Debug support (DBG) RM0090 31 30 29
Page 1391 and 1392: Debug support (DBG) RM0090 Bit 20:1
Page 1399 and 1400: Device electronic signature RM0090
Page 1401 and 1402: A ADC_CCR . . . . . . . . . . . . .
Page 1403 and 1404: DMA_SxM1AR . . . . . . . . . . . .
Page 1405 and 1406: HASH_SR . . . . . . . . . . . . . .
Page 1407: RNG_DR . . . . . . . . . . . . . .
Page 1411 and 1412: Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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