RM0090: Reference manual - STMicroelectronics

RM0090 USB on-the-go high-speed (OTG_HS)
IN data transfers
● Packet write
This section describes how the application writes data packets to the endpoint FIFO in Slave
mode when dedicated transmit FIFOs are enabled.
1. The application can either choose the polling or the interrupt mode.
– In polling mode, the application monitors the status of the endpoint transmit data
FIFO by reading the OTG_HS_DTXFSTSx register, to determine if there is
enough space in the data FIFO.
– In interrupt mode, the application waits for the TXFE interrupt (in
OTG_HS_DIEPINTx) and then reads the OTG_HS_DTXFSTSx register, to
determine if there is enough space in the data FIFO.
– To write a single nonzero length data packet, there must be space to write the
entire packet in the data FIFO.
– To write zero length packet, the application must not look at the FIFO space.
2. Using one of the above mentioned methods, when the application determines that
there is enough space to write a transmit packet, the application must first write into the
endpoint control register, before writing the data into the data FIFO. Typically, the
application, must do a read modify write on the OTG_HS_DIEPCTLx register to avoid
modifying the contents of the register, except for setting the Endpoint Enable bit.
The application can write multiple packets for the same endpoint into the transmit FIFO, if
space is available. For periodic IN endpoints, the application must write packets only for one
micro-frame. It can write packets for the next periodic transaction only after getting transfer
complete for the previous transaction.
● Setting IN endpoint NAK
Internal data flow:
1. When the application sets the IN NAK for a particular endpoint, the core stops
transmitting data on the endpoint, irrespective of data availability in the endpoint’s
transmit FIFO.
2. Nonisochronous IN tokens receive a NAK handshake reply
– Isochronous IN tokens receive a zero-data-length packet reply
3. The core asserts the INEPNE (IN endpoint NAK effective) interrupt in
OTG_HS_DIEPINTx in response to the SNAK bit in OTG_HS_DIEPCTLx.
4. Once this interrupt is seen by the application, the application can assume that the
endpoint is in IN NAK mode. This interrupt can be cleared by the application by setting
the CNAK bit in OTG_HS_DIEPCTLx.
Application programming sequence:
Doc ID 018909 Rev 3 1298/1416