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RM0090: Reference manual - STMicroelectronics

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USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong><br />

f) The core generates the RXFLVL interrupt for the transfer completion status entry<br />

in the receive FIFO.<br />

g) The application must read and ignore the receive packet status when the receive<br />

packet status is not an IN data packet (PKTSTS in GRXSTSR ≠ 0b0010).<br />

h) The core generates the XFRC interrupt as soon as the receive packet status is<br />

read.<br />

i) In response to the XFRC interrupt, disable the channel and stop writing the<br />

OTG_FS_HCCHAR2 register for further requests. The core writes a channel<br />

disable request to the non-periodic request queue as soon as the<br />

OTG_FS_HCCHAR2 register is written.<br />

j) The core generates the RXFLVL interrupt as soon as the halt status is written to<br />

the receive FIFO.<br />

k) Read and ignore the receive packet status.<br />

l) The core generates a CHH interrupt as soon as the halt status is popped from the<br />

receive FIFO.<br />

m) In response to the CHH interrupt, de-allocate the channel for other transfers.<br />

n) Handling non-ACK responses<br />

● Control transactions<br />

Setup, Data, and Status stages of a control transfer must be performed as three<br />

separate transfers. Setup-, Data- or Status-stage OUT transactions are performed<br />

similarly to the bulk OUT transactions explained previously. Data- or Status-stage IN<br />

transactions are performed similarly to the bulk IN transactions explained previously.<br />

For all three stages, the application is expected to set the EPTYP field in<br />

OTG_FS_HCCHAR1 to Control. During the Setup stage, the application is expected to<br />

set the PID field in OTG_FS_HCTSIZ1 to SETUP.<br />

● Interrupt OUT transactions<br />

A typical interrupt OUT operation is shown in Figure 370. The assumptions are:<br />

– The application is attempting to send one packet in every frame (up to 1 maximum<br />

packet size), starting with the odd frame (transfer size = 1 024 bytes)<br />

– The periodic transmit FIFO can hold one packet (1 KB)<br />

– Periodic request queue depth = 4<br />

The sequence of operations is as follows:<br />

a) Initialize and enable channel 1. The application must set the ODDFRM bit in<br />

OTG_FS_HCCHAR1.<br />

b) Write the first packet for channel 1.<br />

c) Along with the last Word write of each packet, the OTG_FS host writes an entry to<br />

the periodic request queue.<br />

d) The OTG_FS host attempts to send an OUT token in the next (odd) frame.<br />

e) The OTG_FS host generates an XFRC interrupt as soon as the last packet is<br />

transmitted successfully.<br />

f) In response to the XFRC interrupt, reinitialize the channel for the next transfer.<br />

1119/1416 Doc ID 018909 Rev 3

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