RM0090: Reference manual - STMicroelectronics

More documents

Recommendations

Info

<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS) OTG_HS host channel-x split control register (OTG_HS_HCSPLTx) (x = 0..11, where x = Channel_number) Address offset: 0x504 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPLITEN Reserved COMPLSPLT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw XACTPOS Bit 31 SPLITEN: Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. Bits 30:17 Reserved, must be kept at reset value. Bit 16 COMPLSPLT: Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. Bits 15:14 XACTPOS: Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 11: All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 01: End. This is the last payload of this transaction (which is larger than 188 bytes) Bits 13:7 HUBADDR: Hub address This field holds the device address of the transaction translator’s hub. Bits 6:0 PRTADDR: Port address This field is the port number of the recipient transaction translator. HUBADDR Doc ID 018909 Rev 3 1212/1416 PRTADDR
USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong> OTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, where x = Channel_number) Address offset: 0x508 + (Channel_number × 0x20) Reset value: 0x0000 0000 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure 382. The application must read this register when the host channels interrupt bit in the Core interrupt register (HCINT bit in OTG_HS_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HS_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HS_HAINT and OTG_HS_GINTSTS registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTERR Bits 31:11 Reserved, must be kept at reset value. Bit 10 DTERR: Data toggle error Bit 9 FRMOR: Frame overrun Bit 8 BBERR: Babble error 1213/1416 Doc ID 018909 Rev 3 rc_ w1 Bit 7 TXERR: Transaction error Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP Bit 6 NYET: Response received interrupt Bit 5 ACK: ACK response received/transmitted interrupt Bit 4 NAK: NAK response received interrupt Bit 3 STALL: STALL response received interrupt Bit 2 AHBERR: AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. Bit 1 CHH: Channel halted Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. Bit 0 XFRC: Transfer completed Transfer completed normally without any errors. FRMOR rc_ w1 BBERR rc_ w1 TXERR rc_ w1 NYET rc_ w1 ACK rc_ w1 NAK rc_ w1 STALL rc_ w1 AHBERR rc_ w1 CHH rc_ w1 XFRC rc_ w1
Page 1 and 2:
RM0090 Reference manual STM32F40x,
Page 3 and 4:
Contents RM0090 3.5.3 Erase . . . .
Page 5 and 6:
Contents RM0090 6.3.1 RCC clock con
Page 7 and 8:
Contents RM0090 7.4.7 GPIO port bit
Page 9 and 10:
Contents RM0090 10.3.4 Falling trig
Page 11 and 12:
Contents RM0090 12.4.2 Independent
Page 13 and 14:
Contents RM0090 14.3.3 Repetition c
Page 15 and 16:
Contents RM0090 15.4.12 TIMx auto-r
Page 17 and 18:
Contents RM0090 17.4.6 TIM6&TIM7 co
Page 19 and 20:
Contents RM0090 22.1 HASH introduct
Page 21 and 22:
Contents RM0090 24.3.3 Tx mailboxes
Page 23 and 24:
Contents RM0090 26.3.14 Hardware fl
Page 25 and 26:
Contents RM0090 28.4.13 SD I/O mode
Page 27 and 28:
Contents RM0090 29.7 Ethernet inter
Page 29 and 30:
Contents RM0090 31.3.1 High-speed O
Page 31 and 32:
Contents RM0090 33.2 Reference ARM
Page 33 and 34:
List of tables RM0090 List of table
Page 35 and 36:
List of tables RM0090 Table 98. Tra
Page 37 and 38:
List of tables RM0090 Table 192. NO
Page 39 and 40:
List of figures RM0090 Figure 49. A
Page 41 and 42:
List of figures RM0090 Figure 151.
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
Documentation conventions RM0090 1
Page 49 and 50:
Memory and bus architecture RM0090
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Embedded Flash memory interface RM0
Page 63 and 64:
Page 65 and 66:
Page 67 and 68:
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
CRC calculation unit RM0090 4 CRC c
Page 89 and 90:
CRC calculation unit RM0090 Bits 7:
Page 91 and 92:
Power control (PWR) RM0090 Figure 7
Page 93 and 94:
Power control (PWR) RM0090 When the
Page 95 and 96:
Power control (PWR) RM0090 mode (se
Page 97 and 98:
Power control (PWR) RM0090 A PVDO f
Page 99 and 100:
Power control (PWR) RM0090 5.3.3 Sl
Page 101 and 102:
Power control (PWR) RM0090 If an ac
Page 103 and 104:
Power control (PWR) RM0090 I/O stat
Page 105 and 106:
Power control (PWR) RM0090 Safe RTC
Page 107 and 108:
Power control (PWR) RM0090 Bit 4 PV
Page 109 and 110:
Power control (PWR) RM0090 5.4.3 PW
Page 111 and 112:
Reset and clock control for (RCC) R
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
General-purpose I/Os (GPIO) RM0090
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
System configuration controller (SY
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
DMA controller (DMA) RM0090 9 DMA c
Page 213 and 214:
DMA controller (DMA) RM0090 9.3 DMA
Page 215 and 216:
DMA controller (DMA) RM0090 Figure
Page 217 and 218:
DMA controller (DMA) RM0090 Table 3
Page 219 and 220:
DMA controller (DMA) RM0090 In dire
Page 221 and 222:
DMA controller (DMA) RM0090 Figure
Page 223 and 224:
DMA controller (DMA) RM0090 memory
Page 225 and 226:
DMA controller (DMA) RM0090 9.3.11
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
DMA controller (DMA) RM0090 9.4 DMA
Page 235 and 236:
DMA controller (DMA) RM0090 Bits 25
Page 237 and 238:
DMA controller (DMA) RM0090 9.5.5 D
Page 239 and 240:
DMA controller (DMA) RM0090 Bits 8
Page 241 and 242:
DMA controller (DMA) RM0090 15 14 1
Page 243 and 244:
Page 245 and 246:
Page 247 and 248:
Interrupts and events RM0090 10 Int
Page 249 and 250:
Interrupts and events RM0090 Table
Page 251 and 252:
Page 253 and 254:
Page 255 and 256:
Page 257 and 258:
Interrupts and events RM0090 genera
Page 259 and 260:
Interrupts and events RM0090 10.3 E
Page 261 and 262:
Interrupts and events RM0090 15 14
Page 263 and 264:
Analog-to-digital converter (ADC) R
Page 265 and 266:
Page 267 and 268:
Page 269 and 270:
Page 271 and 272:
Page 273 and 274:
Page 275 and 276:
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Digital-to-analog converter (DAC) R
Page 309 and 310:
Page 311 and 312:
Page 313 and 314:
Page 315 and 316:
Page 317 and 318:
Page 319 and 320:
Page 321 and 322:
Page 323 and 324:
Page 325 and 326:
Page 327 and 328:
Digital camera interface (DCMI) RM0
Page 329 and 330:
Page 331 and 332:
Page 333 and 334:
Page 335 and 336:
Page 337 and 338:
Page 339 and 340:
Page 341 and 342:
Page 343 and 344:
Page 345 and 346:
Page 347 and 348:
Page 349 and 350:
Advanced-control timers (TIM1&TIM8)
Page 351 and 352:
Page 353 and 354:
Page 355 and 356:
Page 357 and 358:
Page 359 and 360:
Page 361 and 362:
Page 363 and 364:
Page 365 and 366:
Page 367 and 368:
Page 369 and 370:
Page 371 and 372:
Page 373 and 374:
Page 375 and 376:
Page 377 and 378:
Page 379 and 380:
Page 381 and 382:
Page 383 and 384:
Page 385 and 386:
Page 387 and 388:
Page 389 and 390:
Page 391 and 392:
Page 393 and 394:
Page 395 and 396:
Page 397 and 398:
Page 399 and 400:
Page 401 and 402:
Page 403 and 404:
Page 405 and 406:
Page 407 and 408:
Page 409 and 410:
Page 411 and 412:
Page 413 and 414:
Page 415 and 416:
Page 417 and 418:
Page 419 and 420:
General-purpose timers (TIM2 to TIM
Page 421 and 422:
Page 423 and 424:
Page 425 and 426:
Page 427 and 428:
Page 429 and 430:
Page 431 and 432:
Page 433 and 434:
Page 435 and 436:
Page 437 and 438:
Page 439 and 440:
Page 441 and 442:
Page 443 and 444:
Page 445 and 446:
Page 447 and 448:
Page 449 and 450:
Page 451 and 452:
Page 453 and 454:
Page 455 and 456:
Page 457 and 458:
Page 459 and 460:
Page 461 and 462:
Page 463 and 464:
Page 465 and 466:
Page 467 and 468:
Page 469 and 470:
Page 471 and 472:
Page 473 and 474:
Page 475 and 476:
Page 477 and 478:
Page 479 and 480:
Page 481 and 482:
Page 483 and 484:
Page 485 and 486:
Page 487 and 488:
Page 489 and 490:
Page 491 and 492:
Page 493 and 494:
Page 495 and 496:
Page 497 and 498:
Page 499 and 500:
Page 501 and 502:
Page 503 and 504:
Page 505 and 506:
Page 507 and 508:
Page 509 and 510:
Page 511 and 512:
Page 513 and 514:
Page 515 and 516:
Page 517 and 518:
Page 519 and 520:
Page 521 and 522:
Basic timers (TIM6&TIM7) RM0090 17
Page 523 and 524:
Basic timers (TIM6&TIM7) RM0090 Fig
Page 525 and 526:
Basic timers (TIM6&TIM7) RM0090 Fig
Page 527 and 528:
Basic timers (TIM6&TIM7) RM0090 17.
Page 529 and 530:
Page 531 and 532:
Page 533 and 534:
Independent watchdog (IWDG) RM0090
Page 535 and 536:
Independent watchdog (IWDG) RM0090
Page 537 and 538:
Window watchdog (WWDG) RM0090 19 Wi
Page 539 and 540:
Window watchdog (WWDG) RM0090 case,
Page 541 and 542:
Window watchdog (WWDG) RM0090 19.6
Page 543 and 544:
Window watchdog (WWDG) RM0090 19.6.
Page 545 and 546:
Cryptographic processor (CRYP) RM00
Page 547 and 548:
Page 549 and 550:
Page 551 and 552:
Page 553 and 554:
Page 555 and 556:
Page 557 and 558:
Page 559 and 560:
Page 561 and 562:
Page 563 and 564:
Page 565 and 566:
Page 567 and 568:
Page 569 and 570:
Page 571 and 572:
Page 573 and 574:
Page 575 and 576:
Page 577 and 578:
Page 579 and 580:
Page 581 and 582:
Page 583 and 584:
Page 585 and 586:
Page 587 and 588:
Page 589 and 590:
Random number generator (RNG) RM009
Page 591 and 592:
Page 593 and 594:
Page 595 and 596:
Hash processor (HASH) RM0090 22.3 H
Page 597 and 598:
Hash processor (HASH) RM0090 has le
Page 599 and 600:
Hash processor (HASH) RM0090 The le
Page 601 and 602:
Hash processor (HASH) RM0090 with v
Page 603 and 604:
Hash processor (HASH) RM0090 Proced
Page 605 and 606:
Hash processor (HASH) RM0090 Bit 12
Page 607 and 608:
Hash processor (HASH) RM0090 22.4.2
Page 609 and 610:
Hash processor (HASH) RM0090 Bit 3
Page 611 and 612:
Page 613 and 614:
Hash processor (HASH) RM0090 HASH_H
Page 615 and 616:
Page 617 and 618:
Page 619 and 620:
Hash processor (HASH) RM0090 Table
Page 621 and 622:
Real-time clock (RTC) RM0090 23.2 R
Page 623 and 624:
Real-time clock (RTC) RM0090 The as
Page 625 and 626:
Real-time clock (RTC) RM0090 23.3.5
Page 627 and 628:
Real-time clock (RTC) RM0090 RTC_TR
Page 629 and 630:
Real-time clock (RTC) RM0090 window
Page 631 and 632:
Real-time clock (RTC) RM0090 The fo
Page 633 and 634:
Real-time clock (RTC) RM0090 Sectio
Page 635 and 636:
Page 637 and 638:
Real-time clock (RTC) RM0090 23.6 R
Page 639 and 640:
Page 641 and 642:
Real-time clock (RTC) RM0090 Bit 3
Page 643 and 644:
Page 645 and 646:
Page 647 and 648:
Page 649 and 650:
Page 651 and 652:
Page 653 and 654:
Page 655 and 656:
Page 657 and 658:
Page 659 and 660:
Controller area network (bxCAN) RM0
Page 661 and 662:
Page 663 and 664:
Page 665 and 666:
Page 667 and 668:
Page 669 and 670:
Page 671 and 672:
Page 673 and 674:
Page 675 and 676:
Page 677 and 678:
Page 679 and 680:
Page 681 and 682:
Page 683 and 684:
Page 685 and 686:
Page 687 and 688:
Page 689 and 690:
Page 691 and 692:
Page 693 and 694:
Page 695 and 696:
Page 697 and 698:
Page 699 and 700:
Page 701 and 702:
Page 703 and 704:
Inter-integrated circuit (I 2 C) in
Page 705 and 706:
Page 707 and 708:
Page 709 and 710:
Page 711 and 712:
Page 713 and 714:
Page 715 and 716:
Page 717 and 718:
Page 719 and 720:
Page 721 and 722:
Page 723 and 724:
Page 725 and 726:
Page 727 and 728:
Page 729 and 730:
Page 731 and 732:
Page 733 and 734:
Page 735 and 736:
Page 737 and 738:
Page 739 and 740:
Universal synchronous asynchronous
Page 741 and 742:
Page 743 and 744:
Page 745 and 746:
Page 747 and 748:
Page 749 and 750:
Page 751 and 752:
Page 753 and 754:
Page 755 and 756:
Page 757 and 758:
Page 759 and 760:
Page 761 and 762:
Page 763 and 764:
Page 765 and 766:
Page 767 and 768:
Page 769 and 770:
Page 771 and 772:
Page 773 and 774:
Page 775 and 776:
Page 777 and 778:
Page 779 and 780:
Page 781 and 782:
Page 783 and 784:
Page 785 and 786:
Page 787 and 788:
Page 789 and 790:
Page 791 and 792:
Serial peripheral interface (SPI) R
Page 793 and 794:
Page 795 and 796:
Page 797 and 798:
Page 799 and 800:
Page 801 and 802:
Page 803 and 804:
Page 805 and 806:
Page 807 and 808:
Page 809 and 810:
Page 811 and 812:
Page 813 and 814:
Page 815 and 816:
Page 817 and 818:
Page 819 and 820:
Page 821 and 822:
Page 823 and 824:
Page 825 and 826:
Page 827 and 828:
Page 829 and 830:
Page 831 and 832:
Page 833 and 834:
Page 835 and 836:
Page 837 and 838:
Page 839 and 840:
Page 841 and 842:
Page 843 and 844:
Secure digital input/output interfa
Page 845 and 846:
Page 847 and 848:
Page 849 and 850:
Page 851 and 852:
Page 853 and 854:
Page 855 and 856:
Page 857 and 858:
Page 859 and 860:
Page 861 and 862:
Page 863 and 864:
Page 865 and 866:
Page 867 and 868:
Page 869 and 870:
Page 871 and 872:
Page 873 and 874:
Page 875 and 876:
Page 877 and 878:
Page 879 and 880:
Page 881 and 882:
Page 883 and 884:
Page 885 and 886:
Page 887 and 888:
Page 889 and 890:
Page 891 and 892:
Page 893 and 894:
Page 895 and 896:
Page 897 and 898:
Page 899 and 900:
Ethernet (ETH): media access contro
Page 901 and 902:
Page 903 and 904:
Page 905 and 906:
Page 907 and 908:
Page 909 and 910:
Page 911 and 912:
Page 913 and 914:
Page 915 and 916:
Page 917 and 918:
Page 919 and 920:
Page 921 and 922:
Page 923 and 924:
Page 925 and 926:
Page 927 and 928:
Page 929 and 930:
Page 931 and 932:
Page 933 and 934:
Page 935 and 936:
Page 937 and 938:
Page 939 and 940:
Page 941 and 942:
Page 943 and 944:
Page 945 and 946:
Page 947 and 948:
Page 949 and 950:
Page 951 and 952:
Page 953 and 954:
Page 955 and 956:
Page 957 and 958:
Page 959 and 960:
Page 961 and 962:
Page 963 and 964:
Page 965 and 966:
Page 967 and 968:
Page 969 and 970:
Page 971 and 972:
Page 973 and 974:
Page 975 and 976:
Page 977 and 978:
Page 979 and 980:
Page 981 and 982:
Page 983 and 984:
Page 985 and 986:
Page 987 and 988:
Page 989 and 990:
Page 991 and 992:
Page 993 and 994:
Page 995 and 996:
Page 997 and 998:
Page 999 and 1000:
Page 1001 and 1002:
Page 1003 and 1004:
Page 1005 and 1006:
Page 1007 and 1008:
Page 1009 and 1010:
Page 1011 and 1012:
Page 1013 and 1014:
Page 1015 and 1016:
Page 1017 and 1018:
USB on-the-go full-speed (OTG_FS) R
Page 1019 and 1020:
Page 1021 and 1022:
Page 1023 and 1024:
Page 1025 and 1026:
Page 1027 and 1028:
Page 1029 and 1030:
Page 1031 and 1032:
Page 1033 and 1034:
Page 1035 and 1036:
Page 1037 and 1038:
Page 1039 and 1040:
Page 1041 and 1042:
Page 1043 and 1044:
Page 1045 and 1046:
Page 1047 and 1048:
Page 1049 and 1050:
Page 1051 and 1052:
Page 1053 and 1054:
Page 1055 and 1056:
Page 1057 and 1058:
Page 1059 and 1060:
Page 1061 and 1062:
Page 1063 and 1064:
Page 1065 and 1066:
Page 1067 and 1068:
Page 1069 and 1070:
Page 1071 and 1072:
Page 1073 and 1074:
Page 1075 and 1076:
Page 1077 and 1078:
Page 1079 and 1080:
Page 1081 and 1082:
Page 1083 and 1084:
Page 1085 and 1086:
Page 1087 and 1088:
Page 1089 and 1090:
Page 1091 and 1092:
Page 1093 and 1094:
Page 1095 and 1096:
Page 1097 and 1098:
Page 1099 and 1100:
Page 1101 and 1102:
Page 1103 and 1104:
Page 1105 and 1106:
Page 1107 and 1108:
Page 1109 and 1110:
Page 1111 and 1112:
Page 1113 and 1114:
Page 1115 and 1116:
Page 1117 and 1118:
Page 1119 and 1120:
Page 1121 and 1122:
Page 1123 and 1124:
Page 1125 and 1126:
Page 1127 and 1128:
Page 1129 and 1130:
Page 1131 and 1132:
Page 1133 and 1134:
Page 1135 and 1136:
Page 1137 and 1138:
Page 1139 and 1140:
Page 1141 and 1142:
Page 1143 and 1144:
Page 1145 and 1146:
Page 1147 and 1148:
Page 1149 and 1150:
Page 1151 and 1152:
Page 1153 and 1154:
Page 1155 and 1156:
USB on-the-go high-speed (OTG_HS) R
Page 1157 and 1158:
Page 1159 and 1160:
Page 1161 and 1162: USB on-the-go high-speed (OTG_HS) R
Page 1211: USB on-the-go high-speed (OTG_HS) R
Page 1263 and 1264:
Page 1265 and 1266:
Page 1267 and 1268:
Page 1269 and 1270:
Page 1271 and 1272:
Page 1273 and 1274:
Page 1275 and 1276:
Page 1277 and 1278:
Page 1279 and 1280:
Page 1281 and 1282:
Page 1283 and 1284:
Page 1285 and 1286:
Page 1287 and 1288:
Page 1289 and 1290:
Page 1291 and 1292:
Page 1293 and 1294:
Page 1295 and 1296:
Page 1297 and 1298:
Page 1299 and 1300:
Page 1301 and 1302:
Page 1303 and 1304:
Page 1305 and 1306:
Page 1307 and 1308:
Page 1309 and 1310:
Page 1311 and 1312:
Page 1313 and 1314:
Flexible static memory controller (
Page 1315 and 1316:
Page 1317 and 1318:
Page 1319 and 1320:
Page 1321 and 1322:
Page 1323 and 1324:
Page 1325 and 1326:
Page 1327 and 1328:
Page 1329 and 1330:
Page 1331 and 1332:
Page 1333 and 1334:
Page 1335 and 1336:
Page 1337 and 1338:
Page 1339 and 1340:
Page 1341 and 1342:
Page 1343 and 1344:
Page 1345 and 1346:
Page 1347 and 1348:
Page 1349 and 1350:
Page 1351 and 1352:
Page 1353 and 1354:
Page 1355 and 1356:
Page 1357 and 1358:
Page 1359 and 1360:
Page 1361 and 1362:
Page 1363 and 1364:
Page 1365 and 1366:
Page 1367 and 1368:
Debug support (DBG) RM0090 33 Debug
Page 1369 and 1370:
Debug support (DBG) RM0090 Figure 4
Page 1371 and 1372:
Debug support (DBG) RM0090 33.4.3 I
Page 1373 and 1374:
Debug support (DBG) RM0090 Figure 4
Page 1375 and 1376:
Debug support (DBG) RM0090 Only the
Page 1377 and 1378:
Debug support (DBG) RM0090 Table 22
Page 1379 and 1380:
Debug support (DBG) RM0090 Note: No
Page 1381 and 1382:
Debug support (DBG) RM0090 33.9 AHB
Page 1383 and 1384:
Debug support (DBG) RM0090 33.11 Ca
Page 1385 and 1386:
Debug support (DBG) RM0090 For this
Page 1387 and 1388:
Debug support (DBG) RM0090 33.15.3
Page 1389 and 1390:
Debug support (DBG) RM0090 31 30 29
Page 1391 and 1392:
Debug support (DBG) RM0090 Bit 20:1
Page 1393 and 1394:
Page 1395 and 1396:
Page 1397 and 1398:
Page 1399 and 1400:
Device electronic signature RM0090
Page 1401 and 1402:
A ADC_CCR . . . . . . . . . . . . .
Page 1403 and 1404:
DMA_SxM1AR . . . . . . . . . . . .
Page 1405 and 1406:
HASH_SR . . . . . . . . . . . . . .
Page 1407 and 1408:
RNG_DR . . . . . . . . . . . . . .
Page 1409 and 1410:
Revision history RM0090 Revision hi
Page 1411 and 1412:
Revision history RM0090 Table 238.
Page 1413 and 1414:
Page 1415 and 1416:
show all

RM0090: Reference manual - STMicroelectronics

Create successful ePaper yourself

Delete template?

Save as template?