RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS) 31 Table 182. OTG_HS register map and reset values (continued) Offset Register 0xB10 0xB30 0xB34 0xB3C 0xB50 0xB54 0xB5C 0xB70 0xB74 0xB7C 0xE00 OTG_HS_DOE PTSIZ0 Reserved STUP CNT Reserved Refer to Table 2 on page 53 for the register boundary addresses. 31.13 OTG_HS programming model 31.13.1 Core initialization PKTCNT Reserved XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PTSIZ1 Reserved RXDPID/ STUPCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PDMA1 DMAADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PDMAB1 DMABADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PTSIZ2 Reserved RXDPID/ STUPCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PDMA2 DMAADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PDMAB2 DMABADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PTSIZ3 Reserved RXDPID/ STUPCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PDMA3 DMAADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DOE PDMAB3 DMABADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_PCG CCTL Reserved Reset value 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The application must perform the core initialization sequence. If the cable is connected during power-up, the current mode of operation bit in the Core interrupt register (CMOD bit in OTG_HS_GINTSTS) reflects the mode. The OTG_HS controller enters host mode when an “A” plug is connected or peripheral mode when a “B” plug is connected. This section explains the initialization of the OTG_HS controller after power-on. The application must follow the initialization sequence irrespective of host or peripheral mode operation. All core global registers are initialized according to the core’s configuration: Doc ID 018909 Rev 3 1256/1416 PHYSUSP Reserved GATEHCLK STPPCLK
USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong> 1. Program the following fields in the Global AHB configuration (OTG_HS_GAHBCFG) register: – DMA mode bit – AHB burst length field – Global interrupt mask bit GINT = 1 – RxFIFO nonempty (RXFLVL bit in OTG_HS_GINTSTS) – Periodic TxFIFO empty level 2. Program the following fields in OTG_HS_GUSBCFG register: – HNP capable bit – SRP capable bit – FS timeout calibration field – USB turnaround time field 3. The software must unmask the following bits in the GINTMSK register: OTG interrupt mask Mode mismatch interrupt mask 4. The software can read the CMOD bit in OTG_HS_GINTSTS to determine whether the OTG_HS controller is operating in host or peripheral mode. 31.13.2 Host initialization To initialize the core as host, the application must perform the following steps: 1. Program the HPRTINT in GINTMSK to unmask 2. Program the OTG_HS_HCFG register to select full-speed host 3. Program the PPWR bit in OTG_HS_HPRT to 1. This drives VBUS on the USB. 4. Wait for the PCDET interrupt in OTG_HS_HPRT0. This indicates that a device is connecting to the port. 5. Program the PRST bit in OTG_HS_HPRT to 1. This starts the reset process. 6. Wait at least 10 ms for the reset process to complete. 7. Program the PRST bit in OTG_HS_HPRT to 0. 8. Wait for the PENCHNG interrupt in OTG_HS_HPRT. 9. Read the PSPD bit in OTG_HS_HPRT to get the enumerated speed. 10. Program the HFIR register with a value corresponding to the selected PHY clock 1. 11. Program the FSLSPCS field in OTG_FS_HCFG register according to the speed of the detected device read in step 9. If FSLSPCS has been changed, reset the port. 12. Program the OTG_HS_GRXFSIZ register to select the size of the receive FIFO. 13. Program the OTG_HS_GNPTXFSIZ register to select the size and the start address of the nonperiodic transmit FIFO for nonperiodic transactions. 14. Program the OTG_HS_HPTXFSIZ register to select the size and start address of the periodic transmit FIFO for periodic transactions. To communicate with devices, the system software must initialize and enable at least one channel. 1257/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 A PVDO f
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DMA controller (DMA) RM0090 In dire
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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