RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Hash processor (HASH) 22.4.5 HASH digest registers (HASH_HR0..4/5/6/7) Address offset: 0x0C to 0x1C (STM32F40x and STM32F41x), plus 0x310 to 0x32C (STM32F42x and STM32F43x) Reset value: 0x0000 0000 These registers contain the message digest result named as: 1. H0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description Note that in this case, the HASH_H5 to HASH_H7 register is not used, and is read as zero. 2. A, B, C and D, respectively, in the MD5 algorithm description Note that in this case, the HASH_H4 to HASH_H7 register is not used, and is read as zero. 3. H0 to H6, respectively, in the SHA224 algorithm description, Note that in this case, the HASH_H7 register is not used, and is read as zero. 4. H0 to H7, respectively, in the SHA256 algorithm description, If a read access to one of these registers occurs while the HASH core is calculating an intermediate digest or a final message digest (that is when the DCAL bit has been written to 1), then the read is stalled until the completion of the HASH calculation. Note: H0, H1, H2, H3 and H4 mapping are duplicated in two region. HASH_HR0 Address offset: 0x0C and 0x310 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HASH_HR1 Address offset: 0x10 and 0x314 H0 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H0 r r r r r r r r r r r r r r r r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 H1 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H1 r r r r r r r r r r r r r r r r Doc ID 018909 Rev 3 612/1416
Hash processor (HASH) <strong>RM0090</strong> HASH_HR2 Address offset: 0x14 and 0x318 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HASH_HR3 Address offset: 0x18 and 0x31C HASH_HR4 Address offset: 0x1C and 0x320 HASH_HR5 Address offset: 0x324 613/1416 Doc ID 018909 Rev 3 H2 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H2 r r r r r r r r r r r r r r r r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 H3 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H3 r r r r r r r r r r r r r r r r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 H4 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H4 r r r r r r r r r r r r r r r r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 H5 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H5 r r r r r r r r r r r r r r r r
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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