RM0090: Reference manual - STMicroelectronics

RM0090 General-purpose timers (TIM9 to TIM14)
Figure 179. Capture/compare channel 1 main circuit
read CCR1H S
read CCR1L
R
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIM1_EGR
read_in_progress
input
mode
Figure 180. Output stage of capture/compare channel (channel 1)
CNT > CCR1
Output mode
CNT = CCR1 controller
OC1M[2:0]
TIMx_CCMR1
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
16.4.5 Input capture mode
Capture/compare preload register
capture_transfer
OC1_REF
Capture/compare shadow register
capture
APB Bus
MCU-peripheral interface
high
(if 16-bit)
8 8
Counter
low
compare_transfer
To the master mode
controller
write_in_progress
comparator
output
mode
CNT>CCR1
CNT=CCR1
CC1S[1]
CC1S[0]
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
Doc ID 018909 Rev 3 488/1416
0
1
CC1P
TIMx_CCER
S
R
write CCR1H
write CCR1L
OC1PE
OC1PE
UEV
(from time
base unit)
TIM1_CCMR1
Output
enable
circuit
OC1
CC1E TIMx_CCER
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