RM0090: Reference manual - STMicroelectronics

RM0090 Universal synchronous asynchronous receiver transmitter (USART)
26.5 USART mode configuration
Table 120. USART mode configuration (1)
1. X = supported; NA = not applicable.
26.6 USART registers
USART modes USART1 USART2 USART3 UART4 UART5 USART6
Asynchronous mode X X X X X X
Hardware flow control X X X NA NA X
Multibuffer communication (DMA) X X X X X X
Multiprocessor communication X X X X X X
Synchronous X X X NA NA X
Smartcard X X X NA NA X
Half-duplex (single-wire mode) X X X X X X
IrDA X X X X X X
LIN X X X X X X
Refer to Section 1.1 on page 47 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
26.6.1 Status register (USART_SR)
Address offset: 0x00
Reset value: 0x00C0 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CTS
rc_w0
LBD
rc_w0
TXE
r
TC
rc_w0
RXNE
rc_w0
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Bits 31:10 Reserved, must be kept at reset value
Bit 9 CTS: CTS flag
This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared
by software (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3
register.
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line
Note: This bit is not available for UART4 & UART5.
Bit 8 LBD: LIN break detection flag
This bit is set by hardware when the LIN break is detected. It is cleared by software (by
writing it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
Note: An interrupt is generated when LBD=1 if LBDIE=1
Doc ID 018909 Rev 3 778/1416