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RM0090: Reference manual - STMicroelectronics

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USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong><br />

transfers, the HS_OTG host continues fetching the next packet (up to the value<br />

specified in the MC field) before switching to the next channel.<br />

c) The OTG_HS host attempts to send the OUT token at the beginning of the next<br />

odd frame/micro-frame.<br />

d) After successfully transmitting the packet, the OTG_HS host generates a CHH<br />

interrupt.<br />

e) In response to the CHH interrupt, reinitialize the channel for the next transfer.<br />

● Interrupt IN transactions in DMA mode<br />

The sequence of operations (channelx) is as follows:<br />

a) Initialize and enable channel x as explained in Section : Channel initialization.<br />

b) The OTG_HS host writes an IN request to the request queue as soon as the<br />

channel x gets the grant from the arbiter (round-robin with fairness). In highbandwidth<br />

transfers, the OTG_HS host writes consecutive writes up to MC times.<br />

c) The OTG_HS host attempts to send an IN token at the beginning of the next (odd)<br />

frame/micro-frame.<br />

d) As soon the packet is received and written to the receive FIFO, the OTG_HS host<br />

generates a CHH interrupt.<br />

e) In response to the CHH interrupt, reinitialize the channel for the next transfer.<br />

● Isochronous OUT transactions in DMA mode<br />

a) Initialize and enable channel x as explained in Section : Channel initialization.<br />

b) The OTG_HS host starts fetching the first packet as soon as the channel is<br />

enabled, and writes the OUT request along with the last DWORD fetch. In highbandwidth<br />

transfers, the OTG_HS host continues fetching the next packet (up to<br />

the value specified in the MC field) before switching to the next channel.<br />

c) The OTG_HS host attempts to send an OUT token at the beginning of the next<br />

(odd) frame/micro-frame.<br />

d) After successfully transmitting the packet, the HS_OTG host generates a CHH<br />

interrupt.<br />

e) In response to the CHH interrupt, reinitialize the channel for the next transfer.<br />

● Isochronous IN transactions in DMA mode<br />

The sequence of operations ((channel x) is as follows:<br />

a) Initialize and enable channel x as explained in Section : Channel initialization.<br />

b) The OTG_HS host writes an IN request to the request queue as soon as the<br />

channel x gets the grant from the arbiter (round-robin with fairness). In high-<br />

1283/1416 Doc ID 018909 Rev 3

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