RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> General-purpose I/Os (GPIO) 7.3.2 I/O pin multiplexer and mapping The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin. Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers: ● After reset all I/Os are connected to the system’s alternate function 0 (AF0) ● The peripherals’ alternate functions are mapped from AF1 to AF13 ● Cortex-M4F EVENTOUT is mapped on AF15 This structure is shown in Figure 18 below. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages. To use an I/O in a given configuration, proceed as follows: 1. System function Connect the I/O to AF0 and configure it depending on the function used: – JTAG/SWD, after each device reset these pins are assigned as dedicated pins immediately usable by the debugger host (not controlled by the GPIO controller) – RTC_REFIN: this pin should be configured in Input floating mode – MCO1 and MCO2: these pins have to be configured in alternate function mode. Note: You can disable some or all of the JTAG/SWD pins and so release the associated pins for GPIO usage. For more details please refer to Section 6.2.10: Clock-out capability. Doc ID 018909 Rev 3 188/1416
General-purpose I/Os (GPIO) <strong>RM0090</strong> Table 28. Flexible SWJ-DP pin assignment 2. GPIO Available debug ports Configure the desired I/O as output or input in the GPIOx_MODER register. 3. Peripheral alternate function For the ADC and DAC, configure the desired I/O as analog in the GPIOx_MODER register. For other peripherals: – Configure the desired I/O as an alternate function in the GPIOx_MODER register – Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively – Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register 4. EVENTOUT Configure the I/O pin used to output the Cortex-M4F EVENTOUT signal by connecting it to AF15 Note: EVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PH0, PH1 and PI8. Please refer to the “Alternate function mapping” table in the datasheets for the detailed mapping of the system and peripherals’ alternate function I/O pins. 189/1416 Doc ID 018909 Rev 3 PA13 / JTMS/ SWDIO SWJ I/O pin assigned PA14 / JTCK/ SWCLK PA15 / JTDI PB3 / JTDO PB4/ NJTRST Full SWJ (JTAG-DP + SW-DP) - Reset state X X X X X Full SWJ (JTAG-DP + SW-DP) but without NJTRST JTAG-DP Disabled and SW-DP Enabled X X X X X X JTAG-DP Disabled and SW-DP Disabled Released
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 15 14 1
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DMA controller (DMA) RM0090 9.5.11
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DMA controller (DMA) RM0090 Table 4
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Window watchdog (WWDG) RM0090 19.6
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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