RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS) 31 Table 175. OTG_FS register map and reset values (continued) Offset Register 0x560 0x580 0x5A0 0x5C0 0x5E0 0x508 0x528 0x548 0x568 0x588 0x5A8 0x5C8 0x5E8 0x50C 0x52C OTG_FS_HCC HAR3 CHENA CHDIS ODDFRM DAD MCNT EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCC HAR4 CHENA CHDIS ODDFRM DAD MCNT EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCC HAR5 CHENA CHDIS ODDFRM DAD MCNT EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCC HAR6 CHENA CHDIS ODDFRM DAD MCNT EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCC HAR7 CHENA CHDIS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODDFRM DAD MCNT EPTYP LSDEV Reserved EPDIR EPNUM MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN T0 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN T1 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN T2 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN T3 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN T4 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN T5 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN T6 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN T7 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN TMSK0 Reserved DTERRM FRMORM BBERRM TXERRM Doc ID 018909 Rev 3 1104/1416 STALL STALL STALL STALL STALL STALL STALL STALL Reserved CHH Reserved CHH Reserved CHH Reserved CHH Reserved CHH Reserved CHH Reserved CHH Reserved CHH XFRC XFRC XFRC XFRC XFRC XFRC XFRC XFRC NYET ACKM NAKM STALLM Reserved CHHM XFRCM Reset value 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN TMSK1 Reserved DTERRM FRMORM BBERRM TXERRM NYET ACKM NAKM STALLM Reserved CHHM XFRCM Reset value 0 0 0 0 0 0 0 0 0 0
USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong> Table 175. OTG_FS register map and reset values (continued) Offset Register 31 0x54C 0x56C 0x58C 0x5AC 0x5CC 0x5EC 0x510 0x530 0x550 0x570 0x590 0x5B0 0x5D0 0x5F0 OTG_FS_HCIN TMSK2 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN TMSK3 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN TMSK4 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN TMSK5 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN TMSK6 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCIN TMSK7 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCTS IZ0 Reserved 1105/1416 Doc ID 018909 Rev 3 DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCTS IZ1 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCTS IZ2 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCTS IZ3 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCTS IZ4 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCTS IZ5 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCTS IZ6 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCTS IZ7 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800 OTG_FS_DCFG 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 PFIVL BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM DAD NYET ACKM NYET ACKM NYET ACKM NYET ACKM NYET ACKM NYET ACKM NAKM STALLM NAKM STALLM NAKM STALLM NAKM STALLM NAKM STALLM NAKM STALLM Reserved NZLSOHSK Reserved CHHM Reserved CHHM Reserved CHHM Reserved CHHM Reserved CHHM Reserved CHHM DSPD XFRCM XFRCM XFRCM XFRCM XFRCM XFRCM
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Real-time clock (RTC) RM0090 23.2 R
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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