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RM0090: Reference manual - STMicroelectronics

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Secure digital input/output interface (SDIO) <strong>RM0090</strong><br />

For the SD I/O card, the registration process is accomplished as follows:<br />

1. The bus is activated.<br />

2. The SDIO card host sends IO_SEND_OP_COND (CMD5).<br />

3. The cards respond with the contents of their operation condition registers.<br />

4. The incompatible cards are set to the inactive state.<br />

5. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an<br />

address. This new address is called the relative card address (RCA); it is shorter than<br />

the CID and addresses the card. The assigned card changes to the Standby state. The<br />

SDIO card host can reissue this command to change the RCA. The RCA of the card is<br />

the last assigned value.<br />

28.4.5 Block write<br />

During block write (CMD24 - 27) one or more blocks of data are transferred from the host to<br />

the card with a CRC appended to the end of each block by the host. A card supporting block<br />

write is always able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails,<br />

the card indicates the failure on the SDIO_D line and the transferred data are discarded and<br />

not written, and all further transmitted blocks (in multiple block write mode) are ignored.<br />

If the host uses partial blocks whose accumulated length is not block aligned and, block<br />

misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card<br />

will detect the block misalignment error before the beginning of the first misaligned block.<br />

(ADDRESS_ERROR error bit is set in the status register). The write operation will also be<br />

aborted if the host tries to write over a write-protected area. In this case, however, the card<br />

will set the WP_VIOLATION bit.<br />

Programming of the CID and CSD registers does not require a previous block length setting.<br />

The transferred data is also CRC protected. If a part of the CSD or CID register is stored in<br />

ROM, then this unchangeable part must match the corresponding part of the receive buffer.<br />

If this match fails, then the card reports an error and does not change any register contents.<br />

Some cards may require long and unpredictable times to write a block of data. After<br />

receiving a block of data and completing the CRC check, the card begins writing and holds<br />

the SDIO_D line low if its write buffer is full and unable to accept new data from a new<br />

WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS<br />

command (CMD13) at any time, and the card will respond with its status. The<br />

READY_FOR_DATA status bit indicates whether the card can accept new data or whether<br />

the write process is still in progress. The host may deselect the card by issuing CMD7 (to<br />

select a different card), which will place the card in the Disconnect state and release the<br />

SDIO_D line(s) without interrupting the write operation. When selecting the card again, it will<br />

reactivate busy indication by pulling SDIO_D to low if programming is still in progress and<br />

the write buffer is unavailable.<br />

28.4.6 Block read<br />

In Block read mode the basic unit of data transfer is a block whose maximum size is defined<br />

in the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose start and<br />

end addresses are entirely contained within one physical block (as defined by<br />

READ_BL_LEN) may also be transmitted. A CRC is appended to the end of each block,<br />

ensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read and<br />

after completing the transfer, the card returns to the Transfer state.<br />

CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks.<br />

859/1416 Doc ID 018909 Rev 3

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