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RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS)<br />

gating. The dynamic power consumption due to the USB clock switching activity is cut<br />

even if the 48 MHz clock input is kept running by the application<br />

Most of the transceiver is also disabled, and only the part in charge of detecting the<br />

asynchronous resume or remote wakeup event is kept alive.<br />

● Gate HCLK (GATEHCLK bit in OTG_FS_PCGCCTL)<br />

When setting the Gate HCLK bit in the clock gating control register, most of the system<br />

clock domain internal to the OTG_FS core is switched off by clock gating. Only the<br />

register read and write interface is kept alive. The dynamic power consumption due to<br />

the USB clock switching activity is cut even if the system clock is kept running by the<br />

application for other purposes.<br />

● USB system stop<br />

When the OTG_FS is in the USB suspended state, the application may decide to<br />

drastically reduce the overall power consumption by a complete shut down of all the<br />

clock sources in the system. USB System Stop is activated by first setting the Stop<br />

PHY clock bit and then configuring the system deep sleep mode in the power control<br />

system module (PWR).<br />

The OTG_FS core automatically reactivates both system and USB clocks by<br />

asynchronous detection of remote wakeup (as an host) or resume (as a device)<br />

signaling on the USB.<br />

To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS<br />

core.<br />

30.9 Dynamic update of the OTG_FS_HFIR register<br />

The USB core embeds a dynamic trimming capability of micro-SOF framing period in host<br />

mode allowing to synchronize an external device with the micro-SOF frames.<br />

When the OTG_HS_HFIR register is changed within a current micro-SOF frame, the SOF<br />

period correction is applied in the next frame as described in Figure 361.<br />

Figure 361. Updating OTG_FS_HFIR dynamically<br />

SOF<br />

reload<br />

OTG_FS_HFIR<br />

write<br />

OTG_FS_HFIR<br />

value<br />

Frame<br />

timer<br />

1<br />

Old OTG_FS_HIFR value<br />

= 400 periods<br />

400<br />

0<br />

400<br />

399<br />

…<br />

1<br />

0<br />

400<br />

399<br />

OTG_FS_HIFR value<br />

= 450 periods+HIFR write latency<br />

Latency<br />

450<br />

… … …<br />

450<br />

449<br />

New OTG_FS_HIFR value<br />

= 450 periods<br />

Doc ID 018909 Rev 3 1034/1416<br />

1<br />

0<br />

450<br />

449<br />

1<br />

0<br />

450<br />

449<br />

ai184

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