RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> DMA controller (DMA) Figure 25. System implementation of the two DMA controllers (STM32F40x and STM32F41x) To AHB2 peripherals To AHB2 peripherals AHB slave AHB slave DMA controller 2 DMA request MAPPING Arbiter Arbiter FIFO FIFO AHB memory port AHB periph port AHB memory port DMA controller 1 AHB periph port Bus matrix (AHB multilayer) AHB-APB bridge2 (dual AHB) AHB-APB bridge1 (dual AHB) Flash memory 112 KB SRAM AHB2 peripherals External memory controller (FSMC) MS19927V2 1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus only DMA2 streams are able to perform memory-to-memory transfers. DCODE ICODE 16 KB SRAM AHB1 peripherals Doc ID 018909 Rev 3 214/1416 APB1 APB2 APB2 peripherals APB1 peripherals
DMA controller (DMA) <strong>RM0090</strong> Figure 26. System implementation of the two DMA controllers (STM32F42x and STM32F43x) To AHB2 peripherals To AHB2 peripherals AHB slave AHB slave DMA controller 2 DMA request MAPPING DMA controller 1 AHB periph 1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus only DMA2 streams are able to perform memory-to-memory transfers. 9.3.2 DMA transactions A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are softwareprogrammable. Each DMA transfer consists of three operations: ● A loading from the peripheral data register or a location in memory, addressed through the DMA_SxPAR or DMA_SxM0AR register ● A storage of the data loaded to the peripheral data register or a location in memory addressed through the DMA_SxPAR or DMA_SxM0AR register ● A post-decrement of the DMA_SxNDTR register, which contains the number of transactions that still have to be performed 215/1416 Doc ID 018909 Rev 3 Arbiter Arbiter FIFO FIFO AHB memory port AHB periph port AHB memory port port Bus Matrix (AHB multilayer) DCODE ICODE AHB-APB bridge2 (dual AHB) AHB-APB bridge1 (dual AHB) Flash memory 112 KB SRAM 16 KB SRAM 64 KB SRAM AHB1 peripherals APB1 APB2 AHB2 peripherals External memory controller (FSMC) APB2 peripherals APB1 peripherals MS30437V1
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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Analog-to-digital converter (ADC) R
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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