RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Ethernet (ETH): media access control (MAC) with DMA controller 29.3 Ethernet pins Table 158 shows the MAC signals and the corresponding MII/RMII signal mapping. All MAC signals are mapped onto AF11, some signals are mapped onto different I/O pins, and should be configured in Alternate function mode (for more details, refer to Section 7.3.2: I/O pin multiplexer and mapping). Table 158. Alternate function mapping Port AF11 ETH PA0-WKUP ETH_MII_CRS PA1 ETH_MII _RX_CLK / ETH_RMII _REF_CLK PA2 ETH _MDIO PA3 ETH _MII_COL PA7 ETH_MII _RX_DV / ETH_RMII _CRS_DV PB0 ETH _MII_RXD2 PB1 ETH _MII_RXD3 PB5 ETH _PPS_OUT PB8 ETH _MII_TXD3 PB10 ETH_ MII_RX_ER PB11 ETH _MII_TX_EN / ETH _RMII_TX_EN PB12 ETH _MII_TXD0 / ETH _RMII_TXD0 PB13 ETH _MII_TXD1 / ETH _RMII_TXD1 PC1 ETH _MDC PC2 ETH _MII_TXD2 PC3 ETH _MII_TX_CLK PC4 ETH_MII_RXD0 / ETH_RMII_RXD0 PC5 ETH _MII_RXD1/ ETH _RMII_RXD1 PE2 ETH_MII_TXD3 PG8 ETH_PPS_OUT PG11 ETH _MII_TX_EN / ETH _RMII_TX_EN PG13 ETH _MII_TXD0 / ETH _RMII_TXD0 PG14 ETH _MII_TXD1 / ETH _RMII_TXD1 PH2 ETH _MII_CRS PH3 ETH _MII_COL PH6 ETH _MII_RXD2 PH7 ETH _MII_RXD3 PI10 ETH _MII_RX_ER Doc ID 018909 Rev 3 902/1416
Ethernet (ETH): media access control (MAC) with DMA controller <strong>RM0090</strong> 29.4 Ethernet functional description: SMI, MII and RMII The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated DMA controller. It supports both default media-independent interface (MII) and reduced media-independent interface (RMII) through one selection bit (refer to SYSCFG_PMC register). The DMA controller interfaces with the Core and memories through the AHB Master and Slave interfaces. The AHB Master Interface controls data transfers while the AHB Slave interface accesses Control and Status Registers (CSR) space. The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before transmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet frames received from the line until they are transferred to system memory by the DMA. The Ethernet peripheral also includes an SMI to communicate with external PHY. A set of configuration registers permit the user to select the desired mode and features for the MAC and the DMA controller. Note: The AHB clock frequency must be at least 25 MHz when the Ethernet is used. Figure 320. ETH block diagram AHB Slave interface Bus matrix DMA control & status registers Ethernet DMA Operation mode register 2 Kbyte RX FIFO 2 Kbyte TX FIFO Media access control MAC 802.3 Checksum offload MAC control registers 1. For AHB connections please refer to Figure 1: System architecture for STM32F40x and STM32F41x devices and Figure 2: System architecture for STM32F42x and STM32F43x devices. 29.4.1 Station management interface: SMI PTP IEEE1588 PMT MMC The station management interface (SMI) allows the application to access any PHY registers through a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs. The application can select one of the 32 PHYs and one of the 32 registers within any PHY and send control data or receive status information. Only one register in one PHY can be addressed at any given time. Both the MDC clock line and the MDIO data line are implemented as alternate function I/O in the microcontroller: ● MDC: a periodic clock that provides the timing reference for the data transfer at the maximum frequency of 2.5 MHz. The minimum high and low times for MDC must be 903/1416 Doc ID 018909 Rev 3 RMII Interface MII MDC MDIO Select External PHY ai15620c
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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