RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> General-purpose timers (TIM9 to TIM14) 16.6.11 TIM10/11/13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the tables below: Table 81. TIM10/11/13/14 register map and reset values Offset Register 31 0x00 0x08 0x0C 0x10 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 URS TIMx_CR1 Reserved CKD [1:0] Reserved Reset value 0 0 0 0 0 0 TIMx_SMCR Reset value Reserved TIMx_DIER Reserved Reset value 0 0 TIMx_SR Reserved Refer to Table 2 on page 53 for the register boundary addresses. Doc ID 018909 Rev 3 520/1416 CC1OF ARPE Reserved Reset value 0 0 0 0x14 TIMx_EGR Reserved Reset value 0 0 TIMx_CCMR1 Output compare mode Reserved OC1M [2:0] CC1S [1:0] 0x18 Reset value TIMx_CCMR1 Input capture mode Reserved 0 0 0 IC1F[3:0] 0 0 IC1 PSC [1:0] 0 0 CC1S [1:0] Reset value 0 0 0 0 0 0 0 0 0x1C Reserved 0x20 0x24 0x28 0x2C TIMx_CCER Reserved Reset value 0 0 0 TIMx_CNT Reserved CNT[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_PSC Reserved PSC[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_ARR Reserved ARR[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved 0x34 0x38 to 0x4C 0x50 TIMx_CCR1 Reserved CCR1[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_OR Reserved Reserved Reset value 0 0 OC1PE OC1FE CC1NP Reserved CC1P UDIS CEN CC1IE UIE CC1IF UIF CC1G UG TI1_RMP CC1E
Basic timers (TIM6&TIM7) <strong>RM0090</strong> 17 Basic timers (TIM6&TIM7) This section applies to the whole STM32F4xx family, unless otherwise specified. 17.1 TIM6&TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs. The timers are completely independent, and do not share any resources. 17.2 TIM6&TIM7 main features Basic timer (TIM6&TIM7) features include: ● 16-bit auto-reload upcounter ● 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 ● Synchronization circuit to trigger the DAC ● Interrupt/DMA generation on the update event: counter overflow Figure 188. Basic timer block diagram Internal clock (CK_INT) TIMxCLK from RCC 521/1416 Doc ID 018909 Rev 3 U Stop, Clear or up CK_PSC PSC Prescaler CK_CNT ± CNT COUNTER interrupt & DMA output Trigger controller Controller Auto-reload Register Flag Preload registers transferred to active registers on U event according to control bit event U TRGO Reset, Enable, Count, UI to DAC ai14749b
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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