RM0090: Reference manual - STMicroelectronics

RM0090 Secure digital input/output interface (SDIO)
Table 126. SDIO I/O definitions
28.3.1 SDIO adapter
Pin Direction Description
SDIO_CK Output
SDIO_CMD Bidirectional
SDIO_D[7:0] Bidirectional
Figure 313 shows a simplified block diagram of an SDIO adapter.
Figure 313. SDIO adapter
To APB2
interface
SDIO adapter
Adapter
registers
FIFO
The SDIO adapter is a multimedia/secure digital memory card bus master that provides an
interface to a multimedia card stack or to a secure digital memory card. It consists of five
subunits:
● Adapter register block
● Control unit
● Command path
● Data path
● Data FIFO
Note: The adapter registers and FIFO use the APB2 bus clock domain (PCLK2). The control unit,
command path and data path use the SDIO adapter clock domain (SDIOCLK).
Adapter register block
MultiMediaCard/SD/SDIO card clock. This pin is the clock from
host to card.
MultiMediaCard/SD/SDIO card command. This pin is the
bidirectional command/response signal.
MultiMediaCard/SD/SDIO card data. These pins are the
bidirectional databus.
Control unit
Command
path
Data path
PCLK2 SDIOCLK
SDIO_CK
SDIO_CMD
SDIO_D[7:0]
The adapter register block contains all system registers. This block also generates the
signals that clear the static flags in the multimedia card. The clear signals are generated
when 1 is written into the corresponding bit location in the SDIO Clear register.
ai15899
Doc ID 018909 Rev 3 846/1416
Card bus