RM0090: Reference manual - STMicroelectronics

Real-time clock (RTC) RM0090
window around each of the calendar updates (every 1 s). The window equals 7 ck_apre
periods when detecting the first reference clock edge. A smaller window of 3 ck_apre
periods is used for subsequent calendar updates.
Each time the reference clock is detected in the window, the asynchronous prescaler which
outputs the ck_apre clock is forced to reload. This has no effect when the reference clock
and the 1 Hz clock are aligned because the prescaler is being reloaded at the same
moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little
for them to be aligned with the reference clock.
If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window),
the calendar is updated continuously based solely on the LSE clock. The RTC then waits for
the reference clock using a large 7 ck_apre period detection window centered on the
ck_spre edge.
When the reference clock detection is enabled, PREDIV_A and PREDIV_S must be set to
their default values:
● PREDIV_A = 0x007F
● PREVID_S = 0x00FF
Note: The reference clock detection is not available in Standby mode.
Caution: The reference clock detection feature cannot be used in conjunction with the coarse digital
calibration: RTC_CALIBR must be kept at 0x0000 0000 when REFCKON=1.
23.3.10 RTC coarse digital calibration
Two digital calibration methods are available: coarse and smooth calibration. To perform
coarse calibration refer to Section 23.6.7: RTC calibration register (RTC_CALIBR).
The two calibration methods are not intended to be used together, the application must
select one of the two methods. Coarse calibration is provided for compatibly reasons. To
perform smooth calibration refer to Section 23.3.11: RTC smooth digital calibration and the
Section 23.6.16: RTC calibration register (RTC_CALR)
The coarse digital calibration can be used to compensate crystal inaccuracy by adding
(positive calibration) or masking (negative calibration) clock cycles at the output of the
asynchronous prescaler (ck_apre).
Positive and negative calibration are selected by setting the DCS bit in RTC_CALIBR
register to ‘0’ and ‘1’, respectively.
When positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute
(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated
sooner, thereby adjusting the effective RTC frequency to be a bit higher.
When negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute
(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated
later, thereby adjusting the effective RTC frequency to be a bit lower.
DC is configured through bits DC[4:0] of RTC_CALIBR register. This number ranges from 0
to 31 corresponding to a time interval (2xDC) ranging from 0 to 62.
The coarse digital calibration can be configured only in initialization mode, and starts when
the INIT bit is cleared. The full calibration cycle lasts 64 minutes. The first 2xDC minutes of
the 64 -minute cycle are modified as just described.
629/1416 Doc ID 018909 Rev 3