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RM0090: Reference manual - STMicroelectronics

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USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong><br />

Figure 381. Updating OTG_HS_HFIR dynamically<br />

SOF<br />

reload<br />

OTG_HS_HFIR<br />

write<br />

OTG_HS_HFIR<br />

value<br />

Frame<br />

timer<br />

1<br />

400<br />

31.10 FIFO RAM allocation<br />

31.10.1 Peripheral mode<br />

Receive FIFO RAM<br />

For Receive FIFO RAM, the application should allocate RAM for SETUP packets: 10<br />

locations must be reserved in the receive FIFO to receive SETUP packets on control<br />

endpoints. These locations are reserved for SETUP packets and are not used by the core to<br />

write any other data.<br />

One location must be allocated for Global OUT NAK. Status information are also written to<br />

the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet<br />

Size / 4) + 1 must be allocated to receive packets. If a high-bandwidth endpoint or multiple<br />

isochronous endpoints are enabled, at least two spaces of (Largest Packet Size / 4) + 1<br />

must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1<br />

spaces are recommended so that when the previous packet is being transferred to AHB, the<br />

USB can receive the subsequent packet.<br />

Along with each endpoints last packet, transfer complete status information are also pushed<br />

to the FIFO. Typically, one location for each OUT endpoint is recommended.<br />

Transmit FIFO RAM<br />

For Transmit FIFO RAM, the minimum RAM space required for each IN Endpoint Transmit<br />

FIFO is the maximum packet size for this IN endpoint.<br />

Note: More space allocated in the transmit IN Endpoint FIFO results in a better performance on<br />

the USB.<br />

31.10.2 Host mode<br />

Old OTG_HS_HIFR value<br />

= 400 periods<br />

0<br />

400<br />

399<br />

…<br />

Receive FIFO RAM<br />

OTG_HS_HIFR value<br />

= 450 periods+HIFR write latency<br />

Latency<br />

For Receive FIFO RAM allocation, Status information are written to the FIFO along with<br />

each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be<br />

allocated to receive packets. If a high-bandwidth channel or multiple isochronous channels<br />

1171/1416 Doc ID 018909 Rev 3<br />

1<br />

0<br />

400<br />

399<br />

450<br />

New OTG_HS_HIFR value<br />

= 450 periods<br />

… … … …<br />

450<br />

449<br />

1<br />

0<br />

450<br />

449<br />

1<br />

0<br />

450<br />

449<br />

ai18439b

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