RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Inter-integrated circuit (I 2 C) interface 25.6.10 I 2 C FLTR register (I2C_FLTR) Address offset: 0x24 Reset value: 0x0000 The I2C_FLTR is available on STM32F42x and STM32F43x only. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits 15:5 Reserved, must be kept at reset value ANOFF DNF[3:0] rw rw rw rw rw Bit 4 ANOFF: Analog noise filter OFF 0: Analog noise filter enable 1: Analog noise filter disable Note: ANOFF must be configured only when the I2C is disabled (PE = 0). Bits 3:0 DNF[3:0]: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL inputs. The digital filter will suppress the spikes with a length of up to DNF[3:0] * TPCLK1. 0000: Digital noise filter disable 0001: Digital noise filter enabled and filtering capability up to 1* TPCLK1. ... 1111: Digital noise filter enabled and filtering capability up to 15* TPCLK1. Note: DNF[3:0] must be configured only when the I2C is disabled (PE = 0). If the analog filter is also enabled, the digital filter is added to the analog filter. Doc ID 018909 Rev 3 736/1416
Inter-integrated circuit (I 2 C) interface <strong>RM0090</strong> 25.6.11 I 2 C register map The table below provides the I 2 C register map and reset values. Table 104. I 2 C register map and reset values Offset Register 31 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 I2C_CR1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Refer to Table 2 on page 53 for the register boundary addresses table. 737/1416 Doc ID 018909 Rev 3 SWRST Reserved ALERT PEC POS ACK STOP 8 7 6 5 4 3 2 1 0 START NOSTRETCH ENGC ENPEC ENARP SMBTYPE Reserved SMBUS PE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_CR2 Reserved LAST DMAEN ITBUFEN ITEVTEN ITERREN Reserved FREQ[5:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 I2C_OAR1 Reserved ADDMODE Reserved ADD[9:8] ADD[7:1] Reset value 0 0 0 0 0 0 0 0 0 0 0 I2C_OAR2 Reserved ADD2[7:1] Reset value 0 0 0 0 0 0 0 0 I2C_DR Reserved DR[7:0] Reset value 0 0 0 0 0 0 0 0 I2C_SR1 Reserved SMBALERT TIMEOUT Reserved PECERR OVR AF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SR2 Reserved PEC[7:0] ARLO BERR TxE RxNE DUALF SMBHOST Reserved STOPF SMBDEFAULT GENCALL ADD10 BTF ADD0 ENDUAL ADDR SB Reserved TRA BUSY MSL Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_CCR Reserved F/S DUTY Reserved CCR[11:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_TRISE Reserved TRISE[5:0] Reset value 0 0 0 0 1 0 I2C_FLTR Reserved ANOFF DNF[3:0] Reset value 0 0 0 0 0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 RTC_TR
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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