RM0090: Reference manual - STMicroelectronics

RM0090 USB on-the-go high-speed (OTG_HS)
Bits 13:10 TRDT: USB turnaround time
Sets the turnaround time in PHY clocks.
The formula below gives the value of TRDT:
TRDT = 4 × AHB clock frequency+ 1 PHY clock frequency.
For example:
If AHB clock frequency = 72 MHz (PHY Clock frequency = 48 MHz), the TRDT must be set to
9.
If AHB clock frequency = 48 Mhz (PHY Clock frequency = 48 MHz), the TRDT must be set to
5.
Note: Only accessible in peripheral mode.
Bit 9 HNPCAP: HNP-capable
The application uses this bit to control the OTG_HS controller’s HNP capabilities.
0: HNP capability is not enabled
1: HNP capability is enabled
Note: Accessible in both peripheral and host modes.
Bit 8 SRPCAP: SRP-capable
The application uses this bit to control the OTG_HS controller’s SRP capabilities. If the core
operates as a nonSRP-capable B-device, it cannot request the connected A-device (host) to
activate V BUS and start a session.
0: SRP capability is not enabled
1: SRP capability is enabled
Note: Accessible in both peripheral and host modes.
Bit 7 Reserved, must be kept at reset value.
Bit 6 PHSEL: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
0: USB 2.0 high-speed ULPI PHY
1: USB 1.1 full-speed serial transceiver
Bits 5:3 Reserved, must be kept at reset value.
Bits 2:0 TOCAL: FS timeout calibration
The number of PHY clocks that the application programs in this field is added to the fullspeed
interpacket timeout duration in the core to account for any additional delays introduced
by the PHY. This can be required, because the delay introduced by the PHY in generating the
line state condition can vary from one PHY to another.
The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The
application must program this field based on the speed of enumeration. The number of bit
times added per PHY clock is 0.25 bit times.
Doc ID 018909 Rev 3 1186/1416