STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Connectivity line devices: reset and clock control (RCC)
Low-power management reset
There are two ways to generate a low-power management reset:
1. Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting NRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to the STM32F10xxx Flash
programming manual.
7.1.2 Power reset
A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 4)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more
details, refer to Table 53: Vector table for other STM32F10xxx devices on page 172.
Figure 10.
Reset circuit
V DD /V DDA
R PU
External
reset
NRST
Filter
System reset
Pulse
generator
(min 20 µs)
WWDG reset
IWDG reset
Power reset
Software reset
Low-power management reset
ai16095
7.1.3 Backup domain reset
The backup domain has two specific resets that affect only the backup domain (see
Figure 4).
A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. V DD or V BAT power on, if both supplies have previously been powered off.
Doc ID 13902 Rev 9 105/995