STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
26.2.3 Peripheral-mode features
The OTG_FS interface:
●
●
●
●
●
●
has 1 bidirectional control endpoint0
has 3 IN endpoints (EPs) configurable to support Bulk, Interrupt or Isochronous
transfers
has 3 OUT endpoints configurable to support Bulk, Interrupt or Isochronous transfers
manages a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB data
RAM
manages up to 4 dedicated Tx-IN FIFOs (one for each active IN EP) to put less load on
the application
supports the soft disconnect feature
26.3 OTG_FS functional description
Figure 260. Block diagram
Cortex-M3
AHB Peripheral
USB Interrupt
Power&
Clock
CTRL
USB duspend
USB2.0
OTG FS
Core
UTMIFS
OTG
FS
PHY
DP
DM
ID
USB Clock at 48 MHz
System clock
domain
USB clock
domain
V BUS
RAM bus
Universal serial bus
1.25 Kbytes
USB data
FIFOs
ai17106
26.3.1 OTG full-speed core
The USB OTG FS receives the 48 MHz ±0.25% clock from the reset and clock controller
(RCC), via an external quartz. The USB clock is used for driving the 48 MHz domain at fullspeed
(12 Mbit/s) and must be enabled prior to configuring the OTG FS Core.
The CPU reads and writes from/to the OTG FS Core registers through the AHB peripheral
bus. It is informed of USB events through the single USB OTG interrupt line described in
Section 26.13: OTG_FS interrupts.
The CPU submits data over the USB by writing 32-bit words to dedicated OTG_FS locations
(push registers). The data are then automatically stored into Tx-data FIFOs configured
696/995 Doc ID 13902 Rev 9