STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Flexible static memory controller (FSMC)
RM0008
SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)
Address offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank, used for SRAMs, ROMs
and NOR Flash memories. If the EXTMOD bit is set in the FSMC_BCRx register, then this
register is partitioned for write and read access, that is, 2 registers are available: one to
configure read accesses (this register) and one to configure write accesses (FSMC_BWTRx
registers).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ACCMOD
DATLAT
CLKDIV
BUSTURN
DATAST
ADDHLD
ADDSET
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 29:28 ACCMOD: Access mode
Specifies the asynchronous access modes as shown in the timing diagrams. These bits are
taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.
00: access mode A
01: access mode B
10: access mode C
11: access mode D
Bits 27:24 DATLAT (see note below bit descriptions): Data latency (for synchronous burst NOR Flash)
For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
cycles (+2) to issue to the memory before getting the first data:
This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
CRAM, this field must be set to 0
0000: Data latency of 2 CLK clock cycles for first burst access
1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
Bits 23:20 CLKDIV: Clock divide ratio (for CLK signal)
Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
0000: Reserved
0001: CLK period = 2 × HCLK periods
0010: CLK period = 3 × HCLK periods
1111: CLK period = 16 × HCLK periods (default value after reset)
In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
Bits 19:16 BUSTURN: Bus turnaround phase duration
These bits are written by software to introduce the bus turnaround delay after a read access
(only from multiplexed NOR Flash memory) to avoid bus contention if the controller needs to
drive addresses on the databus for the next side-by-side transaction. BUSTURN can be set
to the minimum if the memory system does not include multiplexed memories or if the
slowest memory does not take more than 6 HCLK clock cycles to put the databus in Hi-Z
state:
0000: BUSTURN phase duration = 1 × HCLK clock cycle
...
1111: BUSTURN phase duration = 16 × HCLK clock cycles (default value after reset)
438/995 Doc ID 13902 Rev 9