STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
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RDES2: Receive descriptor Word2
RDES2 contains the address pointer to the first data buffer in the descriptor, or it
contains time stamp data.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBP1 / RTSL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 RBAP1 / RTSL: Receive buffer 1 address pointer / Receive frame time stamp low
These bits take on two different functions: the application uses them to indicate to the DMA
where to store the data in memory, and then after transferring all the data the DMA may use
these bits to pass back time stamp data.
RBAP1: When the software makes this descriptor available to the DMA (at the moment that the
OWN bit is set to 1 in RDES0), these bits indicate the physical address of Buffer 1. There are no
limitations on the buffer address alignment except for the following condition: the DMA uses the
configured value for its address generation when the RDES2 value is used to store the start of
frame. Note that the DMA performs a write operation with the RDES2[3/2/1:0] bits as 0 during the
transfer of the start of frame but the frame data is shifted as per the actual Buffer address pointer. The
DMA ignores RDES2[3/2/1:0] (corresponding to bus width of 128/64/32) if the address pointer is to a
buffer where the middle or last part of the frame is stored.
RTSL: Before it clears the OWN bt in RDES0, the DMA updates this field with the 32 least
significant bits of the time stamp captured for the corresponding receive frame (overwriting the
value for RBAP1). This field has the time stamp only if time stamping is activated for this frame
and if the Last segment control bit (LS) in the descriptor is set.
902/995 Doc ID 13902 Rev 9