STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS) RM0008 Bits 23:16 PTXQSAV: Periodic transmit request queue space available Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. 00: Periodic transmit request queue is full 01: dx1 location available 10: dx2 locations available bxn: dxn locations available (0 dxn 8) Others: Reserved Bits 15:0 PTXFSAVL: Periodic transmit data FIFO space available Indicates the number of free locations available to be written to in the periodic TxFIFO. Values are in terms of 32-bit words 0000: Periodic TxFIFO is full 0001: dx1 word available 0010: dx2 words available bxn: dxn words available (where 0 dxn dx512) bx200: dx512 words available Others: Reserved OTG_FS Host all channels interrupt register (OTG_FS_HAINT) Address offset: 0x414 Reset value: 0x0000 000 When a significant event occurs on a channel, the Host all channels interrupt register interrupts the application using the Host channels interrupt bit of the Core interrupt register (HCINT bit in OTG_FS_GINTSTS). This is shown in Figure 268. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Host channel-x interrupt register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HAINT Reserved r r r r r r r r r r r r r r r r Bits 31:16 Reserved Bits 15:0 HAINT: Channel interrupts One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 746/995 Doc ID 13902 Rev 9
RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS host all channels interrupt mask register (OTG_FS_HAINTMSK) Address offset: 0x418 Reset value: 0x0000 0000 The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HAINTM Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 HAINTM: Channel interrupt mask 0: Masked interrupt 1: Unmasked interrupt One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 OTG_FS host port control and status register (OTG_FS_HPRT) Address offset: 0x440 Reset value: 0x0000 0000 This register is available only in Host mode. Currently, the OTG Host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure 268. The rc_w1 bits in this register can trigger an interrupt to the application through the Host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_FS_GINTSTS). On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PSPD PTCTL PPWR r r rw rw rw rw rw r r rw rs rw rc_ w1 PLSTS Reserved PRST PSUSP PRES POCCHNG POCA r PENCHNG rc_ w1 PENA rc_ w0 PCDET rc_ w1 PCSTS r Bits 31:19 Reserved Bits 18:17 PSPD: Port speed Indicates the speed of the device attached to this port. 01: Full speed 10: Low speed 11: Reserved Doc ID 13902 Rev 9 747/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) transfe
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RM0008 DMA controller (DMA) not sup
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Real-time clock (RTC) RTC pr
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Serial peripheral interface
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RM0008 Universal synchronous asynch
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Debug support (DBG) Note: On
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RM0008 Debug support (DBG) DBGMCU_I
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RM0008 Debug support (DBG) Table 20
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RM0008 Debug support (DBG) Bits 31:
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RM0008 Debug support (DBG) Figure 3
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RM0008 Revision history 30 Revision
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RM0008 Revision history Table 215.
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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