STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Revision history
Table 215.
22-May-2008
continued
Document revision history (continued)
Date Revision Changes
4
continued
In Section 6: Low-, medium- and high-density reset and clock control (RCC)
on page 74:
– LSI calibration on page 80 added
– Figure 7: Reset circuit on page 75 updated
– APB2 peripheral reset register (RCC_APB2RSTR) on page 89 updated
– APB1 peripheral reset register (RCC_APB1RSTR) on page 91 updated
– AHB peripheral clock enable register (RCC_AHBENR) updated
– APB2 peripheral clock enable register (RCC_APB2ENR) updated
– APB1 peripheral clock enable register (RCC_APB1ENR) on page 97
updated (see Section Table 15.: RCC register map and reset values).
– LSERDYIE definition modified in Clock interrupt register (RCC_CIR)
– HSITRIM[4:0] definition modified in Clock control register (RCC_CR)
In Section 8: General-purpose and alternate-function I/Os (GPIOs and
AFIOs) on page 138:
– GPIO ports F and G added
–In Section 8.3: Alternate function I/O and debug configuration (AFIO) on
page 152 remapping for High-density devices added, note modified under
Section 8.3.2, Section 8.3.3 on page 153 modified
– AF remap and debug I/O configuration register (AFIO_MAPR) on
page 159 updated
Updated in Section 9: Interrupts and events on page 169:
– number of maskable interrupt channels
– number of GPIOs (see Figure 21: External interrupt/event GPIO mapping)
In Section 10: DMA controller (DMA) on page 182:
– number of DMA controllers and configurable DMA channels updated
– Figure 22: DMA block diagram in connectivity line devices on page 183
updated, notes added
– Note updated in Section 10.3.2: Arbiter on page 184
– Note updated in Section 10.3.6: Interrupts on page 187
– Figure 23: DMA1 request mapping on page 188 updated
– DMA2 controller on page 189 added
In Section 11: Analog-to-digital converter (ADC) on page 198:
– ADC3 added (Figure 25: Single ADC block diagram on page 200 updated,
Table 65: External trigger for injected channels for ADC3 added, etc.)
Section 12: Digital-to-analog converter (DAC) on page 233 added.
In Section 13: Advanced-control timers (TIM1&TIM8) on page 253:
– Advanced control timer TIM8 added (see Figure 51: Advanced-control
timer block diagram on page 255)
– TS[2:0] modified in Section 13.4.3: TIM1&TIM8 slave mode control
register (TIMx_SMCR) on page 297.
In Section 14: General-purpose timer (TIMx) on page 319:
– TIM5 added
– Figure 99: General-purpose timer block diagram on page 321 updated.
Table 76: TIMx Internal trigger connection on page 359 modified.
Section 15: Basic timers (TIM6&TIM7) on page 375 added.
RTC clock sources specified in Section 16.2: RTC main features on
page 388. Section 16.1: RTC introduction modified.
Section 19: Flexible static memory controller (FSMC) on page 409 added.
Section 20: Secure digital input/output interface (SDIO) on page 456 added.
Doc ID 13902 Rev 9 985/995