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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS)<br />

RM0008<br />

26.14.4 Device-mode registers<br />

OTG_FS device configuration register (OTG_FS_DCFG)<br />

Address offset: 0x800<br />

Reset value: 0x0220 0000<br />

This register configures the core in Device mode after power-on or after certain control<br />

comm<strong>and</strong>s or enumeration. Do not make changes to this register after initial programming.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

PFIVL<br />

DAD<br />

Reserved<br />

NZLSOHSK<br />

DSPD<br />

rw rw rw rw rw rw rw rw rw rw rw<br />

Bits 31:13 Reserved<br />

Bits 12:11 PFIVL: Periodic frame interval<br />

Indicates the time within a frame at which the application must be notified using the end of<br />

periodic frame interrupt. This can be used to determine if all the isochronous traffic for that<br />

frame is complete.<br />

00: 80% of the frame interval<br />

01: 85% of the frame interval<br />

10: 90% of the frame interval<br />

11: 95% of the frame interval<br />

Bits 10:4 DAD: Device address<br />

The application must program this field after every SetAddress control comm<strong>and</strong>.<br />

Bit 3 Reserved<br />

Bit 2 NZLSOHSK: Non-zero-length status OUT h<strong>and</strong>shake<br />

The application can use this field to select the h<strong>and</strong>shake the core sends on receiving a<br />

nonzero-length data packet during the OUT transaction of a control transfer’s Status stage.<br />

1: Send a STALL h<strong>and</strong>shake on a nonzero-length status OUT transaction <strong>and</strong> do not send<br />

the received OUT packet to the application.<br />

0: Send the received OUT packet to the application (zero-length or nonzero-length) <strong>and</strong><br />

send a h<strong>and</strong>shake based on the NAK <strong>and</strong> STALL bits for the endpoint in the Device endpoint<br />

control register.<br />

Bits 1:0 DSPD: Device speed<br />

Indicates the speed at which the application requires the core to enumerate, or the maximum<br />

speed the application can support. However, the actual bus speed is determined only after the<br />

chirp sequence is completed, <strong>and</strong> is based on the speed of the USB host to which the core is<br />

connected.<br />

00: Reserved<br />

01: Reserved<br />

10: Reserved<br />

11: Full speed (USB 1.1 transceiver clock is 48 MHz)<br />

754/995 Doc ID 13902 Rev 9

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